• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.234-237
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• 2001

FeSi2/Si Layer were grown using FeSi2, Si wafer by the chemical transport reactio nmethod. The directoptical energy gap was found to be 0.871eV at 300 K. The Hall effect is a physical effect arising in matter carrying electric current inthe presence of a magnetic field. The effect is named after the American physicist E. H. Hall, who discovered it in 1879. IN this paper, we study electrical properties of FeSi2/Si layer. And then we measured Hall coefficient Hall mobility,carrier density and Hall voltage according to variation magnetic field and temperature, Because of important part for it applicationVarious phase of silicide is formed at the metal-Si interface when transition metal contacts to Si. Silicides belong to metallic or semiconducting according to their electrical and optical properties. Metallic silicides are used as gate electrodes or interconnections in VLSI devices. Semiconducting silicides can be used as a new material for IR detectors because of their narrow energy band gap.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.234-237
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• 2001

FeSi$_2$/Si Layer were grown using FeSi$_2$, Si wafer by the chemical transport reaction method. The directoptical energy gap was found to be 0.871ev at 300 K. The Hall effect is a physical effect arising in matter carrying electric current in the presence of a magnetic field. The effect is named after the American physicist E. H. Hall, who discovered it in 1879. In this paper, we study electrical properties of FeSi$_2$/Si layer And then we measured Hall coefficient Hall mobility, carrier density and Hall voltage according to variation magnetic field and temperature, Because of important Part for it application Various phase of silicide is formed at the metal-Si interface when transition metal contacts to Si. Silicides belong to metallic or semiconducting according to their electrical and optical properties. Metallic silicides are used as gate electrodes or interconnections in VLSI devices. Semiconducting silicides can be used as a new material for IR detectors because of their narrow energy band gap.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.230-233
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• 2001

FeSi$_2$ Layer were grown using FeSi$_2$, Si wafer by the chemical transport reaction method. The directoptical energy gap was found to be 0.87leV at 300 K. The Hall effect is a Physical effect arising in matter carrying electric current in the presence of a magnetic field. The effect is named after the American physicist E.H. Hall, who discovered it in 1879. In this paper, we study electrical properties of FeSi$_2$/Si layer. And then we measured Hall coefficient Hall mobility, carrier density and Hall voltage according to variation magnetic field and temperature, Because of important part for it application various phase of silicide is formed at the metal-Si interface when transition metal contacts to Si. Silicides belong to metallic or semiconducting according to their electrical and optical properties. Metallic silicides are used as gate electrodes or interconnections in VLSI devices. Semiconducting silicides can be used as a new material for IR detectors because of their narrow energy band gap.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.7
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• pp.341-349
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• 2001

본 논문은 N개의 노드로 구성된 파장분할다중화(Wavelength Division Multiplexing) 방식의 Passive Star형 광상호연결망에서 K개의 파장이 사용가능 할 때 패킷 전송 스케쥴링 문제를 다루고 있다. 모든 노드는 파장조율이 가능한 송신기와 특정 파장에 고정된 수신기를 각각 한 개씩 가지고 있으며, 하나의 패킷이 송신기로부터 수신기까지 전송되는 데에 걸리는 시간은 항상 일정하다고 가정한다. 최적의 패킷 전송 스케쥴이란 송신노드 입장에서 임의의 파장에서 다른 파장으로 송신기를 조율하는 데에 따른 지연시간(turning delay)을 고려하여 같은 시간에 최대한 많은 서로 다른 파장을 사용하도록 함과 동시에, 수신노드의 입장에서 수신된 패킷들의 광/전 변환에 따른 지연시간(conversion delay)을 고려하여 패킷의 수신간격을 일정하게 유지함으로써 모든 패킷이 최소시간 내에 전송될 수 있도록 언제 어떤 파장을 사용하여 패킷들을 전송할 것인지 결정하는 것을 말한다. 본 논문에서는 파장조율에 따른 지연시간을 $\delta$로 나타낼 때 모든 노드가 자기 자신을 제외한 다른 모든 노드에 주기적으로 전방송(all-to-all broadcast)을 반복하는 경우에 임의로 주어진 N, K, $\delta$의 값에 대하여 최적의 패킷 전송 스케쥴을 구할 수 있는 알고리즘을 제안하고 있다. 또한, N이 K로 나누어 떨어지면 최적의 전방송 주기는 [NK($\delta$+1)/{$N_2$-N-NK+K$^2$+K}](N-1)임을 증명하였다.

• Korean Chemical Engineering Research
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• v.45 no.5
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• pp.466-472
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• 2007

A technology platform for wafer-level three-dimensional integration circuits (3D-ICs) is presented, and that uses wafer bonding with low-k polymeric adhesives and Cu damascene inter-wafer interconnects. In this work, one of such technical platforms is explained and characterized using a test vehicle of inter-wafer 3D via-chain structures. Electrical and mechanical characterizations of the structure are performed using continuously connected 3D via-chains. Evaluation results of the wafer bonding, which is a necessary process for stacking the wafers and uses low-k dielectrics as polymeric adhesive, are also presented through the wafer bonding between a glass wafer and a silicon wafer. After wafer bonding, three evaluations are conducted; (1) the fraction of bonded area is measured through the optical inspection, (2) the qualitative bond strength test to inspect the separation of the bonded wafers is taken by a razor blade, and (3) the quantitative bond strength is measured by a four point bending. To date, benzocyclobutene (BCB), $Flare^{TM}$, methylsilsesquioxane (MSSQ) and parylene-N were considered as bonding adhesives. Of the candidates, BCB and $Flare^{TM}$ were determined as adhesives after screening tests. By comparing BCB and $Flare^{TM}$, it was deduced that BCB is better as a baseline adhesive. It was because although wafer pairs bonded using $Flare^{TM}$ has a higher bond strength than those using BCB, wafer pairs bonded using BCB is still higher than that at the interface between Cu and porous low-k interlevel dielectrics (ILD), indicating almost 100% of bonded area routinely.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.93-93
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• 2016

Large scale integrated circuits (LSIs) has been improved by the shrinkage of the circuit dimensions. The smaller chip sizes and increase in circuit density require the miniaturization of the line-width and space between metal interconnections. Therefore, an extreme precise control of the critical dimension and pattern profile is necessary to fabricate next generation nano-electronics devices. The pattern profile control of plasma etching with an accuracy of sub-nanometer must be achieved. To realize the etching process which achieves the problem, understanding of the etching mechanism and precise control of the process based on the real-time monitoring of internal plasma parameters such as etching species density, surface temperature of substrate, etc. are very important. For instance, it is known that the etched profiles of organic low dielectric (low-k) films are sensitive to the substrate temperature and density ratio of H and N atoms in the H2/N2 plasma [1]. In this study, we introduced a feedback control of actual substrate temperature and radical density ratio monitored in real time. And then the dependence of etch rates and profiles of organic films have been evaluated based on the substrate temperatures. In this study, organic low-k films were etched by a dual frequency capacitively coupled plasma employing the mixture of H2/N2 gases. A 100-MHz power was supplied to an upper electrode for plasma generation. The Si substrate was electrostatically chucked to a lower electrode biased by supplying a 2-MHz power. To investigate the effects of H and N radical on the etching profile of organic low-k films, absolute H and N atom densities were measured by vacuum ultraviolet absorption spectroscopy [2]. Moreover, using the optical fiber-type low-coherence interferometer [3], substrate temperature has been measured in real time during etching process. From the measurement results, the temperature raised rapidly just after plasma ignition and was gradually saturated. The temporal change of substrate temperature is a crucial issue to control of surface reactions of reactive species. Therefore, by the intervals of on-off of the plasma discharge, the substrate temperature was maintained within ${\pm}1.5^{\circ}C$ from the set value. As a result, the temperatures were kept within $3^{\circ}C$ during the etching process. Then, we etched organic films with line-and-space pattern using this system. The cross-sections of the organic films etched for 50 s with the substrate temperatures at $20^{\circ}C$ and $100^{\circ}C$ were observed by SEM. From the results, they were different in the sidewall profile. It suggests that the reactions on the sidewalls changed according to the substrate temperature. The precise substrate temperature control method with real-time temperature monitoring and intermittent plasma generation was suggested to contribute on realization of fine pattern etching.

• Journal of the Korean Vacuum Society
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• v.15 no.1
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• pp.89-96
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• 2006

Recent ULSI and multilevel structure trends in microelectronic devices minimize the line width down to less than $0.25{\mu}m$, which results in high current densities in thin film interconnections. Under high current densities, an EM(electromigration) induced failure becomes one of the critical problems in a microelectronic device. This study is to improve thin film interconnection materials by investigating the EM characteristics in Ag, Cu, Au, and Al thin films, etc. EM resistance characteristics of Ag, Cu, Au, and Al thin films with high electrical conductivities were investigated by measuring the activation energies from the TTF (Time-to-Failure) analysis. Optical microscope and XPS (X-ray photoelectron spectroscopy) analysis were used for the failure analysis in thin films. Cu thin films showed relatively high activation energy for the electromigration. Thus Cu thin films may be potentially good candidate for the next choice of advanced thin film interconnection materials where high current density and good EM resitance are required. Passivated Al thin films showed the increased MTF(Mean-time-to-Failure) values, that is, the increased EM resistance characteristics due to the dielectric passivation effects at the interface between the dielectric overlayer and the thin film interconnection materials.