• Proceedings of the Optical Society of Korea Conference
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• 1989.02a
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• pp.180-184
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• 1989

Overviews of vertical and horizontal GaAs/AlGaAs OEIC are shown. Researching double Zn diffusion process, we obtain Xj=At1/2-Bd1, where A=2.5${\mu}{\textrm}{m}$/[hr]1/2, B=0.625, of which process is recommended for exact diffusion interface area control of GaAs/AlGaAs. It is proved to be 100A/100A AlAs/GaAs using MOCVD by measurement of photo-luminescence which shows a luminescence peak corresponding to the 798.4nm wavelength calculated values of 38meV ground state above GaAs conduction band.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.4
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• pp.10-21
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• 2003

Recently, the optical subscriber interface module uses the high performance network processor to quickly develop new application services such as MPLS, VPN, RPR and EPON with a short time-to-market. Although a number of vendors are developing the network processor at 2.5Gbps, only the IBM NP4GS3 can provide packet processing with wire-speed at 2.5Gbps. IBM NP4GS3, however, uses its unique speed DASL interface instead of CSIX-Ll interface, which has standardized by M: Forum currently Therefore, we implement an interconnection mechanism to use the switch fabric with CSIX-Ll interface. In this paper, we suggest the architecture and a packet control mechanism supporting interconnection between IBM NP4GS3 DASL and CSIX-Ll switch interface using the common IBM UDASL ASIC and XILINX FPGA.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.189-195
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• 2004

A 10 Gb/s limiting amplifier IC with the emitter area of $1.5{\times}10{\mu}m^2$ for optical transmission system was designed and fabricated with a AIGaAs/GaAs HBTs technology. In this stud)', we evaluated fine pitch bump using WL-CSP (Wafer Level-Chip Scale Packaging) instead of conventional wire bonding for interconnection. For this we developed WL-CSP process and formed fine pitch solder bump with the $40{\mu}m$ diameter and $100{\mu}m$ pitch on bonding pad. To study the effect of WL-CSP, electrical performance was measured and analyzed in wafer and package module using WL-CSP. In a package module, clear and wide eye diagram openings were observed and the riselfall times were about 100ps, and the output" oltage swing was limited to $600mV_{p-p}$ with input voltage ranging from 50 to 500m V. The Small signal gains in wafer and package module were 15.56dB and 14.99dB respectively. It was found that the difference of small signal gain in wafer and package module was less then 0.57dB up to 10GHz and the characteristics of return loss was improved by 5dB in package module. This is due to the short interconnection length by WL-CSP. So, WL-CSP process can be used for millimeter wave GaAs MMIC with the fine pitch pad.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.7
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• pp.56-65
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• 1999

In this paper, a pixelated binary phase grating to generate $5{\times}5$ spots in designed using simple Genetic Algorithm(sGA) composed of selection, crossover, and mutation operators, and it can be applied for the optical interconnection. So as to adapt that GA is a robust and efficient schema, a chromosome is coded as a binary integer of length $32{\times}32$, the ranking method for decreasing the stochastic sampling error is performed, and a single-point crossover having $16{\times}16$ block size is used. A designed grating when the probabillty of mutation is 0.001, the probability of crossover is 0.75 and the population size is 300 has a 74.7[%] high diffraction efficiency and a $1.73{\times}10^{-1}$ uniformity quantitatively.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.10a
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• pp.39-45
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• 2000

A small camera module fabricated by including bare chip bonding methods is utilized to realize advanced mobile devices. One of the driving forces is the TOG (Tape On Glass) bonding method which reduces the packaging size of the image sensor clip. The TOG module is a new thinner and smaller image sensor module, using flip chip interconnection method with the ACP (Anisotropic Conductive Paste). The TOG production process was established by determining the optimum bonding conditions for both optical glass bonding and image sensor clip bonding lo the flexible PCB. The bonding conditions, including sufficient bonding margins, were studied. Another bonding method is the flip chip bonding method for DSP (Digital Signal Processor) chip. A new AC\ulcorner was developed to enable the short resin curing time of 10 sec. The bonding mechanism of the resin curing method was evaluated using FEM analysis. By using these flip chip bonding techniques, small camera module was realized.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.12
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• pp.1353-1361
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• 1992

Holographic optical element(HOE) is fabricated with the properties of lightweight, thin thickness and interconnectivity for free space. Particularly, HOE for optical interconnection and multiple image processing should have a high efficiency and equal spot intensity, Nonlinear equations for 2-dimensional binary phase grating(BPG) structure is solved by computer simulation based on modified Newton method. Computer-generated pattern drawn by plotter is scaled down and translated into the microfilm. After contact printing between the microfilm and silver halide hologram film, phase diffraction grating produces the $5{\times}5$ multiple spots. Experimental results are shown that bleached phase grating has a high efficiency and equal focused beams except central zero order.

• Journal of the Korean Vacuum Society
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• v.15 no.1
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• pp.89-96
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• 2006

Recent ULSI and multilevel structure trends in microelectronic devices minimize the line width down to less than $0.25{\mu}m$, which results in high current densities in thin film interconnections. Under high current densities, an EM(electromigration) induced failure becomes one of the critical problems in a microelectronic device. This study is to improve thin film interconnection materials by investigating the EM characteristics in Ag, Cu, Au, and Al thin films, etc. EM resistance characteristics of Ag, Cu, Au, and Al thin films with high electrical conductivities were investigated by measuring the activation energies from the TTF (Time-to-Failure) analysis. Optical microscope and XPS (X-ray photoelectron spectroscopy) analysis were used for the failure analysis in thin films. Cu thin films showed relatively high activation energy for the electromigration. Thus Cu thin films may be potentially good candidate for the next choice of advanced thin film interconnection materials where high current density and good EM resitance are required. Passivated Al thin films showed the increased MTF(Mean-time-to-Failure) values, that is, the increased EM resistance characteristics due to the dielectric passivation effects at the interface between the dielectric overlayer and the thin film interconnection materials.

• Journal of the Korea Convergence Society
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• v.8 no.8
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• pp.9-15
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• 2017

With the development of semiconductor integration technology, central processing units and storage devices have been miniaturized and performance has been rapidly developed, interconnection network technology is becoming a more important factor in terms of the performance of high performance computing system. In this paper, we analyze the trend of interconnection network technology used in high performance computing. Interconnect technology, which is the most widely used in the Supercomputer Top 500(2017. 06.), is an Infiniband. Recently, Ethernet is the second highest share after InfiniBand due to the emergence of 40/100Gbps Gigabit Ethernet technology. Gigabit Ethernet, where latency performance is lower than InfiniBand, is preferred in cost-effective medium-sized data centers. In addition, top-end HPC systems that demand high performance are devoting themselves from Ethernet and InfiniBand technologies and are attempting to maximize system performance by introducing their own interconnect networks. In the future, high-performance interconnects are expected to utilize silicon-based optical communication technology to exchange data with light.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.131-139
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• 2013

To overcome the limitations in performance and power consumption of traditional electrical interconnection based network-on-chips (NoCs), a hybrid optical network-on-chip (HONoC) architecture using optical interconnects is emerging. However, the HONoC architecture should use circuit-switching scheme owing to the overhead by optical devices, which worsens the latency unfairness problem caused by frequent path collisions. This resultingly exert a bad influence in overall performance of the system. In this paper, we propose a new task mapping algorithm for optimizing latency by reducing path collisions. The proposed algorithm allocates a task to a certain processing element (PE) for the purpose of minimizing path collisions and worst case latencies. Compared to the random mapping technique and the bandwidth-constrained mapping technique, simulation results show the reduction in latency by 43% and 61% in average for each $4{\times}4$ and $8{\times}8$ mesh topology, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.83-93
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• 2014

It is a widespread concern that electrical interconnection based network-on-chip (NoC) will ultimately face the limitation in communication bandwidth, transmission latency and power consumption in the near future. With the development of silicon photonics technology, a hybrid optical network-on-chip (HONoC) which embraces both electrical- and optical interconnect, is emerging as a promising solution to overcome these problems. Today's leading edge systems-on-chips (SoCs) comprise heterogeneous many-cores for higher energy efficiency, therefore, extended study beyond regular topology based NoC is required. This paper proposes an energy and latency optimization topology design technique for HONoC taking into account the traffic characteristics of target applications. The proposed technique is implemented with genetic algorithm and simulation results show the reduction by 13.84% in power loss and 28.14% in average latency, respectively.