• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.774-780
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• 2017

This paper proposes an efficient binary arithmetic encoder hardware architecture for CABAC encoding, which is an entropy coding method of HEVC. CABAC is an entropy coding method that is used in HEVC standard. Entropy coding removes statistical redundancy and supports a high compression ratio of images. However, the binary arithmetic encoder causes a delay in real time processing and parallel processing is difficult because of the high dependency between data. The operation of the proposed CABAC BAE hardware structure is to separate the renormalization and process the conventional iterative algorithm in parallel. The new scheme was designed as a four-stage pipeline structure that can reduce critical path optimally. The proposed CABAC BAE hardware architecture was designed with Verilog HDL and implemented in 65nm technology. Its gate count is 8.07K and maximum operating speed of 769MHz. It processes the four bin per clock cycle. Maximum processing speed increased by 26% from existing hardware architectures.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.6
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• pp.553-561
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• 2012

Existing energy sources convert chemical energy into mechanical energy, while fuel cell directly generates electricity through an electrochemical reaction between hydrogen and oxygen. Therefore, it has a lot of strong points such as high efficiency, zero emission, and etc. In addition, with the development of hydrogen preservation technique, some companies have been researching and releasing portable fuel cell power packs for specific applications like military equipment, automobile, and so on. However, there are some drawbacks to the fuel cell, high cost and slow dynamic response. In order to compensate these weak points, auxiliary energy storages could be applied to the fuel cell system. In this paper, the optimum structure for a 150W portable fuel cell power pack with a battery pack is selected considering the specification of the system, and the design process of main parts is described in detail. Here, main objectives are compact size, simple control, high efficiency, and low cost. Then, an automatic mode change algorithm, which converts the operating mode depending on the states of fuel cell stack, battery pack, and load, is introduced. Finally, performance of the designed prototype using the automatic mode change control is verified through experiments.

• Convergence Security Journal
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• v.16 no.7
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• pp.113-120
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• 2016

This paper presents a new high-speed SHA-1 pipeline architecture having a computation delay close to the maximum critical path delay of the original SHA-1. The typical SHA-1 pipelines are based on either a hash operation or unfolded hash operations. Their throughputs are greatly enhanced by the parallel processing in the pipeline, but the maximum critical path delay will be increased in comparison with the unfolding of all hash operations in each round. The pipeline stage logics in the proposed SHA-1 has the latency is similar with the result of dividing the maximum threshold delay of a round by the number of iterations. Experimental results show that the proposed SHA-1 pipeline structure is 0.99 and 1.62 at the operating speed ratio according to circuit size, which is superior to the conventional structure. The proposed pipeline architecture is expected to be applicable to various cryptographic and signal processing circuits with iterative operations.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.46 no.4
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• pp.51-60
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• 2009

In radio frequency identification(RFID) systems, when an RFID reader uses the same or adjacent frequency with neighbor readers, the interference between the readers may occur, which causes the reader collision and errors in tag recognition. In the previous study on RFID reader anti-collision, the techniques based on Frequency Division Mutiplex(FDM) or Time Division Multiplex(TDM) are proposed. However in these paper, the problem on the condition of RFID reader-to-reader interference considering the distance between interfering readers, frequency and operating time is not define exactly. In this paper, the interference effect is analyzed through RFID reader interference model considering the TDM and FDM, and the optimization problem is defined. To solve this, genetic-resource allocation technique is proposed. Therefore the optimal resource allocation applied RFID environment faithfully is accomplished.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.34-42
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• 2014

This paper presents a low-complexity and high-throughput symbol detector for two-spatial-stream multiple-input multiple-output systems based on the modified maximum-likelihood symbol detection algorithm. In the proposed symbol detector, the cost function is calculated incrementally employing a multi-cycle architecture so as to eliminate the complex multiplications for each symbol, and the slicing operations are performed hierarchically according to the range of constellation points by a pipelined architecture. The proposed architecture exhibits low hardware complexity while supporting complicated modulations such as 256 QAM. In addition, various modulations and antenna configurations are supported flexibly by reconfiguring the pipeline for the slicing operation. The proposed symbol detector is implemented with 38.7K logic gates in a $0.11-{\mu}m$ CMOS process and its throughput is 166 Mbps for $2{\times}$3 16-QAM and 80Mbps for $2{\times}3$ 64-QAM where the operating frequency is 478 MHz.

• Aerospace Engineering and Technology
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• v.3 no.2
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• pp.229-237
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• 2004

In this paper, the design method and algorithms of the signal processor for a multipurpose radar system are analyzed. The signal processor, operating at the two modes-collision avoidance mode and weather mode, has 4 steps of ADC, NCI, STC, CFAR. Several algorithms of NCI and CFAR are analyzed and the optimal design is proposed to the system. CVI and CMLD algorithm have good performance in decreasing the false alarm rate and increasing detection probability, Regarding processor computational capacity, K=12 for CVI, M=16~20, Ko=M-4 for CMLD is suggested. CVI processing needs much time, two or more processors need to be allocated to CVI. So, for the system with four processors, two processors should be allocated to VID of NCI with ADC input and CFAR with STC, and two processors are should be allocated to CVI.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.12 s.103
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• pp.1206-1212
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• 2005

In this paper, we propose a novel antenna structure which uses the electric and magnetic currents so as to eliminate nulls on their radiation pattern. The tag antenna was matched to the conjugate impedance of the commercial tag chip using the modified double T matching network. The radiation efficiency is about $90\%$, and the bandwidth($S_{11}< -10 dB$) is 848${\~}$926 MHz. Also it shows the gain deviation between the maximum and minimum gains about 4 dB at any direction of the tag antenna at the operating frequency. The readable range of the tag is 1.7${\~}$2.4 m for an arbitrary rotation angle of the tag with a commercial tag chip.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.40 no.5
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• pp.297-304
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• 2016

When a control algorithm is developed to protect automotive compressor surges, the simulation model typically selects an empirically determined look-up table. However, it is difficult for a control oriented empirical model to show surge characteristics of the super charger. In this study, a dynamic supercharger model is developed to predict the performance of a centrifugal compressor under dynamic load follow-up. The model is developed using Simulink$^{(R)}$ environment, and is composed of a compressor, throttle body, valves, and chamber. Greitzer's compressor model is used, and the geometric parameters are achieved by the actual supercharger. The simulation model is validated with experimental data. It is shown that compressor surge is effectively predicted by this dynamic compressor model under various operating conditions.

• Journal of Internet Computing and Services
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• v.21 no.1
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• pp.211-219
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• 2020

One of the major advancements of the Fourth Industrial Revolution is the use of Internet of Drones (IoD), which combines the Internet of Things (IoT) and drone technology. IoD technology is especially important for efficiently and economically operating C4ISR operations in actual battlefields supporting various combat situations. The purpose of this study is to solve the problems of limited battery capacity of drones and lack of budgeting criteria for military drone transcription, introduction, and operation. If the mission area is defined and corresponding multi-drone hovering check points and mission completion time limits are set, then an energy and time co-optimized scheduling and operation control scheme is needed. Because such a scheme does not exist, in this paper, a Drone Force Deployment Optimization (DFDO) scheme is proposed to help schedule multi-drone operation scheduling and networked based remote multi-drone control.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.2
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• pp.171-178
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• 2020

Many countries are establishing and operating blended learning that combines the advantages of online and offline education. However, online education lecture-based Mooc courses have a very low level, with a graduation rate of less than 5-10%. Therefore, in order to increase the graduation rate of students taking online Mooc distance education lectures that anyone can easily take lectures anytime, anywhere on the web-based basis, it is necessary to introduce automatic analysis of students' understanding level of lectures and an automatic academic warning system. Moreover, in order to enter an advanced education country, it is necessary to develop an automatic judgment SW for wrong answer rate, automatic summary SW for lectures, and automatic analysis SW education for lecture-based weak subjects based on mixed learning levels. In order to improve this problem, in this paper, we proposed and simulated an automatic summarization system for lecture contents, an automatic warning system for incorrect answers, and an automatic judgment algorithm for weak subjects.