• Journal of IKEEE
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• v.19 no.3
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• pp.455-459
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• 2015

This paper proposes a dispatch unit of GP-GPU with SIMT architecture to support the acceleration of general-purpose operation as well as graphics processing. If all the information of an operand used instructions issued from the warp scheduler is decoded, an unnecessary operand load occurs, resulting in register loads. To resolve this problem, this paper proposes a method that can reduce the operand load and the load on the resister by decoding only the information of the operand using a pre-decoding method. The operand information from the dispatch unit is passed to the operand selection unit with preventing register bank collisions. Thus the overall performance are improved. In the simulation test, the total clock cycles required by processing 10,000 arbitrary instructions issued from the wrap scheduler using ModelSim SE 10.0b are measured. It shows that the application of the dispatch unit equipped with the pre-decoding function proposed in this paper can make an improvement of about 12% in processing performance compared to the conventional method.

• Journal of information and communication convergence engineering
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• v.13 no.1
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• pp.27-35
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• 2015

Multiprecision multiplication is the most expensive operation in public key-based cryptography. Therefore, many multiplication methods have been studied intensively for several decades. In Workshop on Cryptographic Hardware and Embedded Systems 2011 (CHES2011), a novel multiplication method called 'operand caching' was proposed. This method reduces the number of required load instructions by caching the operands. However, it does not provide full operand caching when changing the row of partial products. To overcome this problem, a novel method, that is, 'consecutive operand caching' was proposed in Workshop on Information Security Applications 2012 (WISA2012). It divides a multiplication structure into partial products and reconstructs them to share common operands between previous and next partial products. However, there is still room for improvement; therefore, we propose a finely designed operand-caching mode to minimize useless memory accesses when the first row is changed. Finally, we reduce the number of memory access instructions and boost the speed of the overall multiprecision multiplication for public key cryptography.

• The Transactions of the Korea Information Processing Society
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• v.5 no.6
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• pp.1652-1659
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• 1998

To provide performance gains by reducing the operand referencing latency and data cache bandwidth requirements, we present an operand reference prediction cache (ORPC) which predicts operand value and address translation during the instruction fetch stage. The prediction is verified in the early stage, and thus it minimizes the performance penalty caused by the misprediction. Through the trace-driven simulation of six benchmark programs, the performance improvement by proposed three aRPC stmctures (OfiPC1, OfiPC2. ORPC3)is analysed and validated.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.167-170
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• 2000

This paper describes a novel multi-operand radix-2 signed-digit(SD) adder. The novel multi-operand addition algorithm can eliminate carry propagation chain by dividing the input operands into even place part and odd place part, and adding them each. The multi-operand adder with this algorithm can add six operands in parallel, and is faster than the ordinary method of SD adder binary tree. A hardware model for proposed adder is shown which is implemented by the current-mode MOSFET circuit technology. Simulations have been made by SPICE in order to verify the function of the proposed circuit.

• The Transactions of the Korea Information Processing Society
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• v.7 no.7
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• pp.2196-2203
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• 2000

As processor's operational frequency increases and processors execute multiple instructions per cycle, the processor performance becomes more dependent on the load operand referencing latency and the data dependency. To reduce the operand fetch latency and to increase ILP by breaking the data dependency, we propose a value-address hybrid predictor using a reasonable size prediction buffer and analyse the performance improvement by the proposed predictor. Through the extensive simulation of 5 benchmark programs, the proposed hybrid prediction scheme accurately predicts 62.72% of all loads which are 12.64% higher than the value prediction scheme and show its cost-effectiveness compared to the address predition scheme. In addition, we analyse the performance improvement achieved by the stride management and the history of previous predictions.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.636-639
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• 1988

This paper suggests the operation performing the noise elimination of binary image. The image is read by the scanner. And operand is selected according to the size of input image. Through the Dilation and Erosion, elementary vector operation with selected operand, the noise of input image is eliminated.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.11
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• pp.56-65
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• 2016

In this paper, in order to reduce the delay and area of the partial product accumulation (PPA) of the parallel decimal multiplier, a tree architecture that composed by multi-operand decimal CSAs and improved CLA is proposed. The proposed tree using multi-operand CSAs reduces the partial product quickly. Since the input range of the recoder of CSA is limited, CSA can get the simplest logic. In addition, using the multi-operand decimal CSAs to add decimal numbers that have limited range in specific locations of the specific architecture can reduce the partial products efficiently. Also, final BCD result can be received faster by improving the logic of the decimal CLA. In order to evaluate the performance of the proposed partial product accumulation, synthesis is implemented by using Design Complier with 180 nm COMS technology library. Synthesis results show the delay of the proposed partial product accumulation is reduced by 15.6% and area is reduced by 16.2% comparing with which uses general method. Also, the total delay and area are still reduced despite the delay and area of the CLA are increased.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.19 no.6
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• pp.185-190
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• 2009

As the use of RSA based on chinese remainder theorem(CRT-RSA) is being generalized, the security of CRT-RSA has been important. Since Bellcore researchers introduced the fault attacks on CRT-RSA, various countermeasures have been proposed. In 1999, Shamir firstly proposed a countermeasure using checking procedure. After Shamir's countermeasure was introduced, various countermeasures based on checking procedure have been proposed. However, Shamir's countermeasure was known to be vulnerable to the modified operand attack by Joey et al. in 2001, and the checking procedure was known to be vulnerable to the modified opcode attack by Yen et al. in 2003. Yen et al. proposed a new countermeasure without checking procedure, but their countermeasure was known to be also vulnerable to the modified operand attack by Yen and Kim in 2007. In this paper, we point out that pre, but countermeasures were vulnerable to the modified operand attack or the modified opcode attack.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.6
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• pp.1-8
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• 2003

A novel CORDIC circuit is presented based on a redundant number system eliminating global carry Propagation. The number format employs a new recoding scheme similar to the Booth receding resolving carry problems in addition. A pipelined architecture is introduced having a constant scale factor in its computation of trigonometric functions. The operational time of the circuit is constant independent of the number of operand digits.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.471-474
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• 2000

In this paper, we present multisample DSP coding technique for StarCore, SC 140 DSP. The multisample programming is a pipelining technique that exploits operand reuse both coefficients and variables within kernel. A coefficient or operand is loaded once from memory and then the value may be used by multiple ALUs. It is possible to evaluate one intermediate product from each of four output sample calculations in parallel . Therefore, parallelization has been achieved by processing multiple samples in parallel rather than multiple intermediate products belonging to only one sample. The benefits of decreasing the number of memory moves per sample is to increase the algorithm perforomance. In this paper, the multisample technique has been implemented in FIR filter calculation using Motorola StarCore DSP development tool.