• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.02a
• /
• pp.153-153
• /
• 2010

p-i-n 형 비정질 실리콘 박막 태양전지에서 p층은 창물질(window material)로서 전기 전도도가 크고, 빛 흡수가 적어야한다. p층의 두께가 얇으면 p층 전체가 depletion layer가 되고 충분한 diffusion potential을 얻을 수 없어 open-circuit voltage ($V_{oc}$)가 작아진다. 반대로 p층 두께가 두꺼워지면 빛 흡수가 증가하고, 표면 재결합이 문제가 되어 변환효율이 감소한다. 밴드갭이 큰 물질로 창층을 제작하게 되면 보다 짧은 파장의 입사광이 직접 i층을 비추므로 Short-circuit current ($I_{sc}$) 와 fill factor를 증가시킬 수 있다. 하여 본 연구에서는 기존의 창층으로 사용되는 Boron을 doping한 p-type a-Si:H 대신에 $N_2O$를 첨가한 p-type a-$SiO_x$:H의 $N_2O$ flow rate에 따른 밴드갭의 변화에 관한 연구를 수행하였다. p-type a-$SiO_x$:H Layer는 $SiH_4$, $H_2$, $N_2O$, $B_2H_6$ 가스를 혼합하여 증착하게 되는데 $SiH_4$, 가스와 $H_2$ 가스의 혼합비는 1:20, $B_2H_6$ 농도는 0.5%로 고정 하였으며 $N_2O$의 flow rate을 가변하며 증착하였다. $N_2O$의 가변조건은 5에서 50sccm으로 가변하여 증착하며 일반적으로 사용되는 RF-PECVD (13.56MHz)를 이용하였고 증착 온도는 175도, 전극간의 거리는 40mm, 파워와 압력은 30W, 700mTorr로 고정하여 진행하였다. 전기적 특성을 알아보기 위해 eagle 2000 Glass를 사용하였고 구조적 특성은 p-type wafer를 사용하여 각각 대략 200nm의 두께로 증착하였다. 증착 두께는 Ellipsometry를 이용하였으며 전기 전도도는 Agilent사의 4156c를 구조적특성은 FT-IR을 사용하여 측정하였다. Conductivity(${\sigma}_d$)는 $N_2O$가 증가함에 따라 $8.73\;{\times}\;10^{-6}$에서 $5.06\;{\times}\;10^{-7}$으로 감소하였고 optical bandgap ($E_{opt}$)은 1.71eV에서 2.0eV로 증가함을 알 수 있었다. 또한 reflective index(n)의 경우는 4.32에서 3.52로 감소함을 나타내었다. 기존의 p-type a-Si:H에 비해 상당한 $E_{opt}$을 가지므로 빛 흡수에 의한 손실을 줄임으로서 $V_oc$를 향상 시킬 수 있으며 동시에 짧은 파장에서의 입사광이 직접 i층을 비추므로 $I_{sc}$와 FF를 향상 시킬 수 있으리라 예상된다. 다소 낮은 전도도만 개선한다면 고효율의 박막 태양전지를 제작 할 수 있을 것으로 기대된다.

• Journal of Powder Materials
• /
• v.31 no.1
• /
• pp.16-22
• /
• 2024

Composite-based piezoelectric devices are extensively studied to develop sustainable power supply and self-powered devices owing to their excellent mechanical durability and output performance. In this study, we design a lead-free piezoelectric nanocomposite utilizing (Ba_0.85 Ca_0.15)(Ti_0.9Zr_0.1)O₃ (BCTZ) nanomaterials for realizing highly flexible energy harvesters. To improve the output performance of the devices, we incorporate porous BCTZ nanowires (NWs) into the nanoparticle (NP)-based piezoelectric nanocomposite. BCTZ NPs and NWs are synthesized through the solid-state reaction and sol-gel-based electrospinning, respectively; subsequently, they are dispersed inside a polyimide matrix. The output performance of the energy harvesters is measured using an optimized measurement system during repetitive mechanical deformation by varying the composition of the NPs and NWs. A nanocomposite-based energy harvester with 4:1 weight ratio generates the maximum open-circuit voltage and short-circuit current of 0.83 V and 0.28 ㎂, respectively. In this study, self-powered devices are constructed with enhanced output performance by using piezoelectric energy harvesting for application in flexible and wearable devices.

• Journal of the Korean Vacuum Society
• /
• v.22 no.1
• /
• pp.37-44
• /
• 2013

In order to investigate an influence of carrier trap by quantum dots (QDs) on the solar parameters, in this study, the $p^+-QD-n/n^+$ solar cells with InAs/GaAs QD active layers are fabricated, and their characteristics are investigated and compared with those of a GaAs matrix solar cell (MSC). Two different types of QD structures, the Stranski-Krastanow (SK) QD and the quasi-monolayer (QML) QD, have been introduced for the QD solar cells, and the parameters (open-circuit voltage ($V_{OC}$), short-cirucuit current ($I_{SC}$), fill factor (FF), conversion efficiency (CE)) are determined from the current-voltage characteristic curves under a standard solar illumination (AM1.5). In SK-QSC, while FF of 80.0% is similar to that of MSC (80.3%), $V_{OC}$ and $J_{SC}$ are reduced by 0.03 V and $2.6mA/cm^2$, respectively. CE is lowered by 2.6% as results of reduced $V_{OC}$ and $J_{SC}$, which is due to a carrier trap into QDs. Though another alternative structure of QML-QD to be expected to relieve the carrier trap have been firstly tried for QSC in this study, it shows negative results contrary to our expectations.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.3
• /
• pp.69-76
• /
• 2008

This work proposes a 12b 1kS/s 65uA 0.35um CMOS algorithmic ADC for sensor interface applications such as accelerometers and gyro sensors requiring high resolution, ultra-low power, and small size simultaneously. The proposed ADC is based on an algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. Two versions of ADCs are fabricated with a conventional open-loop sampling scheme and a closed-loop sampling scheme to investigate the effects of offset and 1/f noise during dynamic operation. Switched bias power-reduction techniques and bias circuit sharing reduce the power consumption of amplifiers in the SHA and MDAC. The current and voltage references are implemented on chip with optional of-chip voltage references for low-power SoC applications. The prototype ADC in a 0.35um 2P4M CMOS technology demonstrates a measured DNL and INL within 0.78LSB and 2.24LSB, and shows a maximum SNDR and SFDR of 60dB and 70dB in versionl, and 63dB and 75dB in version2 at 1kS/s. The versionl and version2 ADCs with an active die area of $0.78mm^2$ and $0.81mm^2$ consume 0.163mW and 0.176mW at 1kS/s and 2.5V, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.34 no.4
• /
• pp.251-255
• /
• 2021

a-Si is commonly considered as a primary candidate for the formation of passivation layer in heterojunction (HIT) solar cells. However, there are some problems when using this material such as significant losses due to recombination and parasitic absorption. To reduce these problems, a wide bandgap material is needed. A wide bandgap has a positive influence on effective transmittance, reduction of the parasitic absorption, and prevention of unnecessary epitaxial growth. In this paper, the adoption of a-SiO_x:H as the intrinsic layer was discussed. To increase lifetime and conductivity, oxygen concentration control is crucial because it is correlated with the thickness, bonding defect, interface density (D_it), and band offset. A thick oxygen-rich layer causes the lifetime and the implied open-circuit voltage to drop. Furthermore the thicker the layer gets, the more free hydrogen atoms are etched in thin films, which worsens the passivation quality and the efficiency of solar cells. Previous studies revealed that the lifetime and the implied voltage decreased when the a-SiOx thickness went beyond around 9 nm. In addition to this, oxygen acted as a defect in the intrinsic layer. The D_it increased up to an oxygen rate on the order of 8%. Beyond 8%, the D_it was constant. By controlling the oxygen concentration properly and achieving a thin layer, high-efficiency HIT solar cells can be fabricated.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.35 no.6
• /
• pp.603-609
• /
• 2022

Passivation quality is mainly governed by epitaxial growth of crystalline silicon wafer surface. Void-rich intrinsic a-Si:H interfacial layer could offer higher resistivity of the c-Si surface and hence a better device efficiency as well. To reduce the resistivity of the contact area, a modification of void-rich intrinsic layer of a-Si:H towards more ordered state with a higher density is adopted by adapting its thickness and reducing its series resistance significantly, but it slightly decreases passivation quality. Higher resistance is not dominated by asymmetric effects like different band offsets for electrons or holes. In this study, multilayer of intrinsic a-Si:H layers were used. The first one with a void-rich was a-Si:H(I₁) and the next one a-SiO_x:H(I₂) were used, where a-SiO_x:H(I₂) had relatively larger band gap of ~2.07 eV than that of a-Si:H (I₁). Using a-SiO_x:H as I₂ layer was expected to increase transparency, which could lead to an easy carrier transport. Also, higher implied voltage than the conventional structure was expected. This means that the a-SiO_x:H could be a promising material for a high-quality passivation of c-Si. In addition, the i-a-SiO_x:H microstructure can help the carrier transportation through tunneling and thermal emission.

• Korean Journal of Materials Research
• /
• v.3 no.6
• /
• pp.614-623
• /
• 1993

Electrical characteristics of LiF-$Li_{2}O-B_{2}O_{3}-P_{2}O_5$ glasses with fixed $Li_2O$ content have been investigated by using AC impedance spectroscopy. Part of the total lithium ions present in these glasses contributes to conduction, and the changes in electrical conductivity with composition was inconsistent with the weak electrolyte model. The power law could not be used to determine the hopping ion concentration in these glasses. Both mobile carrier density and mobility have been modified as Li were added in the form of LiF. The formation of $(B-O-P)^-,di^-$, and metaborate group gave additional available sites for Li+ diffusion causing the enhancement of conductivity. The observed maximum conductivity was $2.43 \times 10^{-4}$S/cm at $150^{\circ}C$ at the composition containing 8mol% LiF. The decomposion potential amounted to 5.94V. The Li/glass electrolyte/$TiS_2$ solid-state cell showed open circuit voltage of 3.14V and energy density of 22 Wh/Kg at $150^{\circ}C$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.12
• /
• pp.53-60
• /
• 2005

This work proposes a 10b 100 MS/s $1.4\;mm^2$ CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs with 1.2 Vp-p at 10b accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 um CMOS shows the maximum measured DNL and INL of 0.59 LSB and 0.77 LSB, respectively. The ADC demonstrates the SNDR of 54 dB, the SFDR of 62 dB, and the power dissipation of 56 mW at 100 MS/s.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2016.02a
• /
• pp.154.2-154.2
• /
• 2016

In this work, we introduce a solution-processed CdS interlayer for use in inverted bulk heterojunction (BHJ) solar cells, and compare this material to a series of standard organic and inorganic cathode interlayers. Different combinations of solution-processed CdS, ZnO and conjugated polyelectrolyte (CPE) layers were compared as cathode interlayers on ITO substrates to construct inverted solar cells based on $PTB7:PC_{71}BM$ and a $P3HT:PC_{61}BM$ as photoactive layers. Introduction of a CdS interlayer significantly improved the power conversion efficiency (PCE) of inverted $PTB7:PC_{71}BM$ devices from 2.0% to 4.9%, however, this efficiency was still fairly low compared to benchmark ZnO or CPE interlayers due to a low open circuit voltage ($V_{OC}$), stemming from the deep conduction band energy of CdS. The $V_{OC}$ was greatly improved by introducing an interfacial dipole (CPE) layer on top of the CdS layer, yielding outstanding diode characteristics and a PCE of 6.8%. The best performing interlayer, however, was a single CPE layer alone, which yielded a $V_{OC}$ of 0.727 V, a FF of 63.2%, and a PCE of 7.89%. Using $P3HT:PC_{61}BM$ as an active layer, similar trends were observed. Solar cells without the cathode interlayer yielded a PCE of 0.46% with a poor $V_{OC}$ of 0.197 V and FF of 34.3%. In contrast, the use of hybrid ZnO/CPE layer as the cathode interlayer considerably improved the $V_{OC}$ of 0.599 V and FF of 53.3%, resulting the PCE of 2.99%. Our results indicate that the CdS layer yields excellent diode characteristics, however, performs slightly worse than benchmark ZnO and CPE layers in solar cell devices due to parasitic absorption below 550 nm. These results suggest that the hybrid inorganic/organic interlayer materials are promising candidates as cathode interlayers for high efficiency inverted solar cells through the modification of interface contacts.

• Journal of the Korean Electrochemical Society
• /
• v.18 no.1
• /
• pp.38-44
• /
• 2015

This review article summarizes the recent progress of quantum dot (QD)-sensitized solar cells based on mesoporous $TiO_2$ thin films. From the intrinsic characteristics of nanoscale inorganic QDs with various compositions, it was possible to construct a variety of 3rd-generation thin film solar cells by solution process. Depending on preparation methods, colloidal QD sensitizers are pre-prepared for later deposition onto the surface of $TiO_2$ or in-situ deposition of QDs from chemical bath is done for direct growth of QD sensitizers over substrates. Recently, colloidal QD sensitizers have shown an overall power conversion efficiency of ~7% by a very precise control of composition while a representative CdS/CdSe from chemical bath deposition have done ~5% with polysulfide electrolytes. In the near future, it is necessary to carry out systematic investigations for developing new hole-conducting materials and controlling interfaces within the cell, thus leading to an enhancement of both open-circuit voltage and fill factor while keeping the current high value of photocurrents from QDs towards more efficient and stable QD-sensitized solar cells.