• Journal of the Korean Society for Precision Engineering
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• v.22 no.2
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• pp.60-69
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• 2005

In electrostatic suspension system of thin plates like a silicon wafer or an aluminum disk for hard disk applications, the lateral restoring force exerted on a suspended object plays an important role since the lateral motion of the suspended object, owing to the inherently stable restoring forces, can be passively stabilized without any active control of it. This paper reports about the measurement apparatus of the lateral restoring force originating from a relative translation of the suspended object with respect to the electrodes-for-suspension. An approximate calculation of the lateral force in disk-shaped objects, the structure of the measurement apparatus, a measurement method, stabilization condition and the guideline in designing the measurement apparatus are described. Experimental results obtained by using a 3.5-inch aluminum disk as a suspended object are presented as well in order to assess the magnitude of lateral force and stiffness, and also verify the usefulness of the measurement apparatus.

• Applied Microscopy
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• v.52
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• pp.1.1-1.8
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• 2022

As semiconductor device architecture develops, from planar field-effect transistors (FET) to FinFET and gate-all-around (GAA), there is an increased need to measure 3D structure sidewalls precisely. Here, we present a 3-Dimensional Atomic Force Microscope (3D-AFM), a powerful 3D metrology tool to measure the sidewall roughness (SWR) of vertical and undercut structures. First, we measured three different dies repeatedly to calculate reproducibility in die level. Reproducible results were derived with a relative standard deviation under 2%. Second, we measured 13 different dies, including the center and edge of the wafer, to analyze SWR distribution in wafer level and reliable results were measured. All analysis was performed using a novel algorithm, including auto fattening, sidewall detection, and SWR calculation. In addition, SWR automatic analysis software was implemented to reduce analysis time and to provide standard analysis. The results suggest that our 3D-AFM, based on the tilted Z scanner, will enable an advanced methodology for automated 3D measurement and analysis.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.95-100
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• 2006

The GaAs-on-insulator (GOI) wafer fabrication technique has been developed by using ion-cut process, based on hydrogen ion implantation and wafer direct bonding techniques. The hydrogen ion implantation condition for the ion-cut process in GaAs and the associated implantation mechanism have been investigated in this paper. Depth distribution of hydrogen atoms and the corresponding lattice disorder in (100) GaAs wafers produced by 40 keV hydrogen ion implantation were studied by SIMS and RBS/channeling analysis, respectively. In addition, the formation of platelets in the as-implanted GaAs and their microscopic evolution with annealing in the damaged layer was also studied by cross-sectional TEM analysis. The influence of the ion fluence, the implantation temperature and subsequent annealing on blistering and/or flaking was studied, and the optimum conditions for achieving blistering/splitting only after post-implantation annealing were determined. It was found that the new optimum implant temperature window for the GaAs ion-cut lie in $120{\sim}160^{\circ}C$, which is markedly lower than the previously reported window probably due to the inaccuracy in temperature measurement in most of the other implanters.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.11
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• pp.953-957
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• 2002

Single crystal 3C-SiC (cubic silicon carbide) thin-films were deposited on Si(100) wafer up to the thickness of 4.3 ${\mu}{\textrm}{m}$ by APCVD (atmospheric pressure chemical vapor deposition) method using HMDS (hexamethyildisilane; ｛CH$_{3}$｝$_{6}$ Si$_{2}$) at 135$0^{\circ}C$. The HMDS flow rate was 0.5 sccm and the carrier gas flow rate was 2.5 slm. The HMDS flow rate was important to get a mirror-like crystal surface. The growth rate of the 3C-SiC film was 4.3 ${\mu}{\textrm}{m}$/hr. The 3C-SiC epitaxial film grown on Si(100) wafer was characterized by XRD (X-ray diffraction), AFM (atomic force microscopy), RHEED (reflection high energy electron diffraction), XPS (X-ray photoelecron spectroscopy), and Raman scattering, respectively. Two distinct phonon modes of TO (transverse optical) near 796 $cm^{-1}$ / and LO (longitudinal optical) near 974$\pm$1 $cm^{-1}$ / of 3C-SiC were observed by Raman scattering measurement. The heteroepitaxially grown film was identified as the single crystal 3C-SiC phase by XRD spectra (2$\theta$=41.5。).).

• Journal of the Microelectronics and Packaging Society
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• v.22 no.3
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• pp.19-23
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• 2015

In this study, two types of Au/TiW bump samples were fabricated by the electroplating process onto Al/Si and SiN/Si wafers for the COG (Chip On Glass) packaging. TiW was used as the UBM (Under Bump Metallurgy) material of the Au bump and it was deposited by a sputtering method under the sputtering powers ranges from 500 to 5000 Watt. We investigated the delamination phenomenas for the prepared samples as a function of the input sputtering powers. The stable interfacial adhesion condition was found to be 1500 Watt in sputtering power. In addition, the SAICAS (Surface And Interfacial Cutting Analysis System) measurement was used to find the adhesion strength of Au bumps for the prepared samples. TiW UBM films were deposited at the 1500 Watt sputtering power. As a results, there was a similar adhesion strengths between TiW/Au interfacial films on Al/Si and SiN/Si wafers. However, the adhesion strength of TiW UBM sputtering films on Al and SiN under films were 2.2 times differences, indicating 0.475 kN/m for Al/Si wafer and 0.093 kN/m for SiN/Si wafer, respectively.

• Journal of the Korean Vacuum Society
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• v.10 no.3
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• pp.361-367
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• 2001

Recently, Chemical Mechanical Polishing(CMP) has become a leading planarization technique as a method for silicon wafer planarization that can meet the more stringent lithographic requirement of planarity for the future submicron device manufacturing. The SOI(Silicon On Insulator) wafer has received considerable attention as bulk-alternative wafer to improve the performance of semiconductor devices. In this paper, the objective of study is to investigate Material Removal Rate(MRR) and surface micro-roughness effects of slurry and pad in the CMP process. When particle size of slurry is increased, Material Removal rate increase. Surface micro-roughness is greater influenced by pad than by particle size of slurry. As a result of AM measurement, surface micro-roughness was improved from 27 $\AA$ Rms to 0.64 $\AA$Rms.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.5
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• pp.358-363
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• 2010

The polishing pad is important element for polishing characteristic such as material removal rate(MRR) and within wafer non-uniformity(WIWNU) in the chemical mechanical planarization(CMP). The result of the viscoelasticity measurement shows that 1st elastic modulus is increased and 2nd elastic modulus is decreased when the top pad is thickened. The finite element analysis(FEA) was conducted to predict characteristic of polishing behavior according to the pad thickness. The result of polishing experiment was similar with the FEA, and it shows that the 1st elastic modulus affects instantaneous deformation of pad related to MRR. And the 2nd elastic modulus has an effect on WIWNU due to the viscoelasticity deformation of pad.

• Korean Journal of Optics and Photonics
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• v.14 no.5
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• pp.504-508
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• 2003

We present a new point-diffraction interferometer, which has been devised for the three-dimensional profile measurement of light scattering rough surfaces. The interferometer system has multiple sources of two-point-diffraction and a CCD camera composed of an array of two-dimensional photodetectors. Each diffraction source is an independent two-point-diffraction interferometer made of a pair of single-mode optical fibers, which are housed in a ceramic ferrule to emit two spherical wave fronts by means of diffraction at their free ends. The two spherical wave fronts then interfere with each other and subsequently generate a unique fringe pattern on the test surface. A He-Ne source provides coherent light to the two fibers through a 2${\times}$l optical coupler, and one of the fibers is elongated by use of a piezoelectric tube to produce phase shifting. The xyz coordinates of the target surface are determined by fitting the measured phase data into a global model of multilateration. Measurement has been performed for the warpage inspection of chip scale packages (CSPs) that are tape-mounted on ball grid arrays (BGAs) and backside profile of a silicon wafer in the middle of integrated-circuit fabrication process. When a diagonal profile is measured across the wafer, the maximum discrepancy turns out to be 5.6 ${\mu}{\textrm}{m}$ with a standard deviation of 1.5 ${\mu}{\textrm}{m}$.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.346.2-346.2
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• 2016

The rear side contact recombination in the crystalline silicon solar cell could be reduced by back surface field. We formed polycrystalline silicon as a back surface field through crystallization of amorphous silicon. A thin silicon oxide applied to the passivation layer. We used quasi-steady-state photoconductance measurement to analyze electrical properties with various annealing condition. And, blister formed on surface of wafer during the annealing process. We observed the blister after varied annealing process with wafer of various surface. Shape and density of blister is influenced by various annealing temperature and process time. As the annealing temperature became higher, the average diameter of blister is decreased and total number of blister is increased. The sample with the $600^{\circ}C$ annealing temperature and 1 min annealing time exhibited the highest implied open circuit voltage and lifetime. We predicted that the various shape and density of blister affects the lifetime and implied open circuit voltage.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.7
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• pp.76-84
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• 1994

The characteristics of 3 inch wafer scale GaAs epitaxial wafer grown by molecular beam epitaxy for LSI process application were studied. The thickness and doping uniformity are characterized and discussed. The growth temperature and growth rate were $600^{\circ}C$ by pyrometer, and 1 $\mu$m/h, respectively. It was found that thickness and doping uniformity were 3.97% and 4.74% respectively across the full 3 inch diameter GaAs epitaxial layer. Also, ungated MESFETs have been fabricated and saturation current measurement showed 4.5% uniformity on 3 inch, epitaxial layer, but uniformity of threshold voltage increase up to 9.2% after recess process for MESFET device.