• Korean Journal of Materials Research
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• v.8 no.10
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• pp.890-897
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• 1998

The direct wafer bonding between n-InP(001) wafer and the ${Si}_3N_4$(200 nm) film grown on the InP wafer by PECVD method was investigated. The surface states of InP wafer and ${Si}_3N_4$/InP which strongly depend upon the direct wafer bonding strength between them when they are brought into contact, were characterized by the contact angle measurement technique and atomic force microscopy. When InP wafer was etched by $50{\%}$ HF, contact angle was $5^{\circ}$ and RMS roughness was $1.54{\AA}$. When ${Si}_3N_4$ was etched by ammonia solution, RMS roughness was $3.11{\AA}$. The considerable amount of initial bonding strength between InP wafer and ${Si}_3N_4$/InP was observed when the two wafer was contacted after the etching process by $50{\%}$ HF and ammonia solution respectively. The bonded specimen was heat treated in $H^2$ or $N^2$, ambient at the temperature of $580^{\circ}C$-$680^{\circ}C$ for lhr. The bonding state was confirmed by SAT(Scannig Acoustic Tomography). The bonding strength was measured by shear force measurement of ${Si}_3N_4$/InP to InP wafer increased up to the same level of PECVD interface. The direct wafer bonding interface and ${Si}_3N_4$/InP PECVD interface were chracterized by TEM and AES.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.12 no.3
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• pp.120-125
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• 2002

Si-wafers for solar cells were cast in a size of $50{\times}46{\times}0.5{\textrm}{mm}^3$ by vacuum casting method. The graphite mold coated by BN powder, which was to prevent the reaction of carbon with the molten silicon, was used. Without coating, the wetting and reaction of Si melt to graphite mold was very severe. In the case of BN coating, SiC was formed in the shape of tiny islands at the surface of Si wafer by the reaction between Si-melt and carbon of the graphite mold on the high temperature. The grain size was about 1 mm. The efficiency of Si solar cell was lower than that of Si solar cell fabricated on commercial single and poly crystalline Si wafer. The reason of low efficiency was discussed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.11-16
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• 2008

In this paper, firstly we made of the rapid thermal processor equipment with the specifically useful structure to measure wafer stress. Secondly we made of the laser interferometry to inspect the wafer surface curvature based on the large deformation theory. And then the wafer surface fringe image was obtained by experiment, and the full field stress distribution of wafer surface comes into view by signal processing with thining and pitch mapping. After wafer was ground by 1mm and polished from the back side to get easily deformation, and it was heated by three to four times thermal treatments at about 1000 degree temperature. Finally the severe deformation between wafer before and after the heat treatment was shown.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.2
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• pp.62-67
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• 2000

The uniformity of temperature on a wafer is one of the most important parameters to control the RTP (Rapid Thermal Process) with proper input signals. Since it is impossible to achieve the uniformity of temperature without exact estimation of temperature at all points on the wafer, the difficulty of understanding internal dynamics and structural complexities of the RTP is a primary obstacle to accurately measure the distributed temperatures on the wafer. Furthermore, it is also hard to accomplish desirable estimation because only few pyrometers have been commonly available in the general equipments. In the paper, a thermal model based on the chamber geometry of the AST SHS200 RTP system is developed to effectively control the thermal uniformity on the wafer. First of all, the estimation method of one-point measurement is developed, which is properly extended to the case of multi-point measurements. This thermal model is validated through certain simulation and experiments. The work can be usefully contributed to building a run-by-run or a real-time controls of the RTP.

• Proceedings of the KSME Conference
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• 2003.11a
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• pp.1816-1821
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• 2003

The sapphire wafer for blue light emitting device was manufactured by the implementation of the chemical and mechanical polishing process. The surface polishing of crystalline sapphire wafer was characterized by zeta potential measurement. The reduction process with the alkali slurry provides the surface chemical reaction with sapphire atoms. The poly-urethane pad also provides the frictional force to take out the chemically-reacted surface layers. The surface roughness was measured by the atomic force microscope and the crystalline quality was characterized by the double crystal X -ray diffraction analysis.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.7 no.3
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• pp.521-527
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• 1995

The average particle deposition velocity toward a vertical wafer surface in a vertical airflow chamber was measured by a wafer surface scanner(PMS Model SAS-3600). Polystyrene latex(PSL) spheres with diameters between 0.3 and $0.8{\mu}m$ were used. To examine the effect of the airflow velocity on the deposition velocity, experiments were conducted for three vertical airflow velocities ; 20, 30, 50cm/s. Experimental data of particle deposition velocity were compared with those given by prediction model suggested by Liu and Ahn(1987).

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2007.04a
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• pp.111-113
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• 2007

Thermal conductivities of copper thin films on silicon wafer was obtained from temperature distribution on the surface of wafer measured by radiation thermometry, when sample was heated with constant temperature ate the both ends in a vacuum and dissipate heat by radiation heat transfer into an environment.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1921-1923
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• 2001

In this work, an array of resistance temperature detector(RTD) was fabricated inside the microchannel in order to investigate in-situ flow characteristics. A rectangular straight microchannel, integrated with RTD's for temperature sensing and a heat source for generating the temperature gradient along the channel. were fabricated with the dimension of $200{\mu}m(W){\times}{\mu}m(D){\times}$48mm(L), while RTD measured precise temperatures at the inside-channel wall. 4" $525{\pm}25{\mu}m$ thick P-type <100> Si wafer was used as a substrate. For the fabrication of RTDs. 5300$\AA$ thick Pt/Ti layer was sputtered on a Pyrex glass wafer. Finally, glass wafer was bonded with Si wafer by anodic bonding, therefore RTD was located inside the microchannel. The temperature distribution inside the fabricated microchannel was obtained from 4 point probe measurements and Dl water is used as a working fluid. Temperature distribution inside the microchannel was measured as a function of mass flow rate and heat flux. As a result, precise temperatures inside the microchannel could be obtained. In conclusion, this novel temperature distribution measurement system will be very useful to the accurate analysis of the flow characteristics in the microchannel.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.825-831
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• 2006

As an increase of chip complexity and level of chip integration, chip input/output (I/O) pad pitches are also drastically reduced. With arrival of high complexity SoC (System on Chip) and SiP (System in Package) products, conventional horizontal type probe card showed its limitation on probing density for wafer level test. To enhance probing density, we proposed new vertical type probe card that has the $70{\mu}m$ probe needle with tungsten wire in $80{\mu}m$ micro-drilled hole in ceramic board. To minimize alignment error, micro-drilling conditions are optimized and epoxy-hardening conditions are also optimized to minimize planarity changes. To apply wafer level test for target devices (T5365 256M SDRAM), designed probe card was characterized by probe needle tension for test, contact resistance measurement, leakage current measurement and the planarity test. Compare to conventional probe card with minimum pitch of $50{\sim}125{\mu}m\;and\;2\;{\Omega}$ of average contact resistance, designed probe card showed only $22{\mu}$ of minimum pitch and $1.5{\Omega}$ of average contact resistance. And also, with the nature of vertical probing style, it showed comparably small contact scratch and it can be applied to bumping type chip test.

• Proceedings of the Korean Vacuum Society Conference
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• 1998.02a
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• pp.114-115
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• 1998

Photoreflectance (pR) measurement h have been employed to study the uniformity of G GaAs!Si 3" wafer. The PR shows the energy of l light and heavy hole even at room temperature. F From the observed energy of LH and HH, it can b be seen that the center of the wafer is more s stressed than the 뼈ge. On the basis of biaxial t tensile stress the higher and lower. transitions are a attributed to heavy and light hole respectively.vely.