• Journal of the Korea Safety Management & Science
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• v.10 no.4
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• pp.189-198
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• 2008

At present, companies write daily work record or use bar-code in order to collect distribution flow data in real time. However, it needs additional works to check the record or read the bar-code with a scanner. In this case, human error could decrease accuracy of data and it would cause problems in reliability. To solve this problem, RFID (Radio Frequency Identification) is introduced in many automatic recognition sector recently. RFID is a technology that identification data is inserted into micro-mini IC chip and recognize, trace, and manage object, animal, or person using wireless frequency. This is being emerged as the core technology in future ubiquitous environment. This study is intended to suggest RFID application method in franchise business. Traceability and visibility of individual product are supplied based on EPCglobal network. It includes DW system which supplies various assessment data about product in supply chain, financial transaction system which is based on product transaction and position information, and RFID middleware which refines and divides product data from RFID tag. With the suggested application methods, individual product's profile data are supplied in real time and it would boost reliability to customer and make effective cooperation with existing operation systems (SCM, CRM, and e-Business) possible.

• Transactions on Electrical and Electronic Materials
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• v.9 no.3
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• pp.123-127
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• 2008

The paper is to solve the problem of existing audio signal transfer system which has a difficulties of system organization and the increase of additional install cost and unfriendly interior. To solve the existing system, we drew the new audio signal transfer system based on PLC and evaluated it. A transmitter and a receiver were designed using the PLC chip INT5500CS. An audio signal transfer system was configured with a CD player to which audio signals are sent from the transmitter and a speaker connected to the receiver. For performance evaluation of this system, a USBPre external sound card and Smaart Live 5 which is a PC-based sound measuring program were added. As a result of our experiment, the measured signal level is $2{\sim}3$ dB lower than reference signal, latency is 16.69 ms, and the specific character of coherency is bad in high frequency band. Otherwise, this system transmits and receives signals over 90 % in good condition as a result of measuring pink noise, frequency (1 kHz), and phase, magnitude. In view of the result so far achieved, the system designed this study has excellent performance, it resolves defect of existing audio signal transfer system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.71-82
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• 2004

Recently, network model inspired by social insect behavior attracts the public attention. The AntNet is an adaptive and distributed routing algorithm using mobile agents, called ants, that mimic the activities of social insect. In this paper. we present a new hardware architecture to realize an AntNet-based routing in practical system on a chip application. The modified AntNet algorithm for hardware implementation is compared with the original algorithm on the various traffic patterns and topologies. Implementation results show that the proposed architecture is suitable and efficient to realize adaptive routing based on the AntNet.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.11
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• pp.32-40
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• 2016

IEEE 802.15.4 is the one of the protocols for radio communication in a personal area network. Because of low cost and low power communication for IoT communication, it requires the highest optimization level in the implementation. Recently, the studies of location aware algorithm based on IEEE802.15.4 standard has been achieved. Location estimation is performed basically in equal consideration of reference node information and blind node information. However, an error is not calculated in this algorithm despite the fact that the coordinates of the estimated location of the blind node include an error. In this paper, we enhanced a conventual maximum likelihood estimation using weighted coefficient and implement the hardwired location aware engine for small code size and low power consumption. On the field test using test-beds, the suggested hardware based location awareness method results better accuracy by 10 percents and reduces both calculation and memory access by 30 percents, which improves the systems power consumption.

• ETRI Journal
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• v.26 no.3
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• pp.229-240
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• 2004

This paper reports on our development of a dual-mode transceiver for a CMOS high-rate Bluetooth system-onchip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front-end. It is designed for both the normal-rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high-rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual-path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual-mode system. The transceiver requires none of the external image-rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order onchip filters. The chip is fabricated on a $6.5-mm^{2}$ die using a standard $0.25-{\mu}m$ CMOS technology. Experimental results show an in-band image-rejection ratio of 40 dB, an IIP3 of -5 dBm, and a sensitivity of -77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive ${\pi}/4-diffrential$ quadrature phase-shift keying $({\pi}/4-DQPSK)$ mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5-V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low-cost, multi-mode, high-speed wireless personal area network.

• Korean Journal of Materials Research
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• v.10 no.6
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• pp.430-436
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• 2000

In this paper, we have studied the effect of constituent ratio NiO, CuO and doped with B-Bi-Zn on proper-ties(microstructure, density, shrinkage, permeability as a function of frequency, etc.) of hexagonal-ferrite for high fre- quency chip-inductor material about several GHz. The permeability were analyzed by impedance analyzer(100 kHz∼ 40 MHz) and network analyzed(30 MHz∼3 GHz). As a result of the characteristics. the B-Bi-Zn glass ceramic was used to lower the sintering temperature for additive as function of frequency from 100kHz to 1.8 GHz showed con-stant tends. The maximum imaginary value of complex permeability was observed near the resonance frequency of 2 GHz.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.4 s.316
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• pp.1-9
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• 2007

An embedded system is implemented in this work by removing PCMCIA dedicate controller chip from ARM processor based embedded Linux system. In this paper, we propose PCMCIA interface architecture by using Ad hoc methods for wireless network. The proposed system is developed based on S3C2410A processor and it is interfaced with PCMCIA socket by using combinational digital logic circuits. It is interesting to observe that Ad hoc interface provides $97.9%{\sim}102.49%$ performance when compared with dedicate controller systems. The results indicate that the proposed method simplifies the system without loss of performance.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.3
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• pp.230-235
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• 2004

This paper describes FPGA implementation of a pointer interpreter which can support a synchronization of SDH(or SONET)-based transmission network. The pointer interpreter consists of a pointer-word extractor and a pointer-word interpreter The pointer-word extractor which is composed of mod-6480 counter, shift register and pointer synchronizing block, finds out the H1 and H2 pointer word from a 51.84 Mb/s AU-3/STS-1 data frame and then performs the synchronizing with a 6.48 Mb/s by dividing them in 8. Based on the extracted pointer word, pointer-word interpreter analyzes pointer states such LOP, AIS and NORM according to pointer state-transition algorithm. It consists of a majority vote, a pointer word valid/invalid check, a pointer justification, and a pointer state check. The simulation results of Xilinx Virtex XCV200PQ240 FPGA chip shows the exact pointer word extraction and correct decision of pointer status based on extracted pointer word. The proposed pointer interpreter is suitable for pointer interpretation of 155 Mb/s STM-1/STS-3 frame.

• Nuclear Engineering and Technology
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• v.54 no.7
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• pp.2444-2452
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• 2022

The field-programmable gate array (FPGA) is gaining popularity in industrial automation such as nuclear power plant instrumentation and control (I&C) systems due to the benefits of having non-existence of operating system, minimum software errors, and minimum common reason failures. Separate functions can be processed individually and in parallel on the same integrated circuit using FPGAs in comparison to the conventional microprocessor-based systems used in any plant operations. The use of FPGAs offers the potential to minimize complexity and the accompanying difficulty of securing regulatory approval, as well as provide superior protection against obsolescence. Wireless sensor networks (WSNs) are a new technology for acquiring and processing plant data wirelessly in which sensor nodes are configured for real-time signal processing, data acquisition, and monitoring. ZigBee (IEEE 802.15.4) is an open worldwide standard for minimum power, low-cost machine-to-machine (M2M), and internet of things (IoT) enabled wireless network communication. It is always a challenge to follow the specific topology when different Zigbee nodes are placed in a large network such as a plant. The research article focuses on the hardware chip design of different topological structures supported by ZigBee that can be used for monitoring and controlling the different operations of the plant and evaluates the performance in Vitex-5 FPGA hardware. The research work presents a strategy for configuring FPGA with ZigBee sensor nodes when communicating in a large area such as an industrial plant for real-time monitoring.

• International Journal of Aeronautical and Space Sciences
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• v.18 no.4
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• pp.675-687
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• 2017

In the aerospace industry, we have produced various models according to operational conditions and the environment after development of the base model is completed. Therefore, when design change is necessary, there are modification and updating costs of the circuit whenever environment variables change. For these reasons, recently, in various fields, system designs that can flexibly respond to changing environmental conditions using field programmable gate arrays (FPGAs) are attracting attention, and the rapidly changing aerospace industry also uses FPGAs to organize the system environment. In this paper, we design the controller area network (CAN) intellectual property (IP) protocol used instead of the avionics protocol that includes ARINC-429 and MIL-STD-1553, which are not suitable for small unmanned aerial vehicle (UAV) systems at the register transistor logic (RTL) level, which does not depend on the FPGA vender, and we verify the performance. Consequentially, a Spartan 6 FPGA model-based system on chip (SoC) including an embedded system is constructed by using the designed CAN communications IP and Xilinx Microblaze, and the configured SoC only recorded an average 32% logic element usage rate in the Spartan 6 FPGA model.