• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
• /
• 2005.05a
• /
• pp.270-274
• /
• 2005

The human beings have increased concern about Energy saving and alternative energy. The power demand has increased the growth of industry and the improvement of life. We have to explore alternate energy sources and utilize effectively domestic resources. The lighting equipments developed Energy saving by using an electric ballast. The load installation should be promoted to rational power management, according to the network, inteligent, and high-function. Therefore, this paper has studied the method of energy saving and consulting.

• Journal of Computing Science and Engineering
• /
• v.6 no.4
• /
• pp.257-266
• /
• 2012

This paper overviews clock design problems related to the circuit reliability in deep submicron design technology. The topics include the clock polarity assignment problem for reducing peak power/ground noise, clock mesh network design problem for tolerating clock delay variation, electromagnetic interference aware clock optimization problem, adjustable delay buffer allocation and assignment problem to support multiple voltage mode designs, and the state encoding problem for reducing peak current in sequential elements. The last topic belongs to finite state machine (FSM) design and is not directly related to the clock design, but it can be viewed that reducing noise at the sequential elements driven by clock signal is contained in the spectrum of reliable circuit design from the clock source down to sequential elements.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
• /
• 2002.11a
• /
• pp.11-15
• /
• 2002

3 V, 2.46GHz Low Noise Amplifier (LNA) have been designed for standard 0.35$\mu\textrm{m}$ CMOS process with one poly and four metal layers. This design includes on-chip biasing, matching network and multilayer spiral inductors. The single-ended amplifier provides a forward gain of 20.5dB with a noise figure 3.35dB, and an IIP3 of -6dBm while drawing 59mW total Power consumption

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.6 no.4
• /
• pp.275-280
• /
• 2006

We propose Doherty power amplifier structure which can be integrated in Silicon RF ICs. Doherty power amplifiers are widely used in RF transmitters, because of their high Power Added Efficiency (PAE) and good linearity. In this paper, it is proposed that a method to replace the quarter wavelength coupler with IQ up-conversion mixers to achieve 90 degree phase shift, which allows on-chip Doherty amplifier. This idea is implemented and manufactured in CMOS 5 GHz band direct-conversion RF transmitter. We measured a 3dB improvement output RF power and linearity.

• Bulletin of the Korean Chemical Society
• /
• v.34 no.4
• /
• pp.1175-1180
• /
• 2013

A microfabricated electrochemical cell comprising PDMS-based microchannel and in-channel gold microelectrodes was fabricated as a sensitive and a miniature alternative to the conventional electroanalytical systems. A reproducible fabrication procedure enabled patterning of multiple microelectrodes integrated within a PDMS-based fluidic network. The active area of each electrode was $200{\mu}m{\times}200{\mu}m$ with a gap of $200{\mu}m$ between the electrodes which resulted in a higher signal to noise ratio. Also, the PDMS layer served the purpose of shielding the electrical interferences to the measurements. Analytes such as potassium ferrocyanide; amino acid: cysteine and nucleoside: guanosine were characterized using the fabricated cell. The microchip was comparable to bulk electrochemical systems and its applicability was also demonstrated with flow injection based rapid amperometric detection of DNA samples. The device so developed shall find use as a disposable electrochemical cell for rapid and sensitive analysis of electroactive species in various industrial and research applications.

• Proceedings of the KIPE Conference
• /
• 2005.07a
• /
• pp.182-184
• /
• 2005

The human beings have Increased concern about Energy saving and alternative energy. The power demand has increased the growth of industry and the improvement of life We have to explore alternate energy sources and utilize effectively domestic resources. The lighting equipments developed Energy saving by using an electric ballast. The load installation should be promoted to rational power management, according to the network, intelligent, and high-function. Therefore, this paper has studied the method of energy saving and consulting.

• Proceedings of the KIEE Conference
• /
• 1998.07c
• /
• pp.838-840
• /
• 1998

The power demand has increased the groth of industry and improvement of life. Otherwise the power supply is more difficult. because of regional egoism, reinforcement for environment, and investment of money. The load installation should be promoted to rational power management, according to the network, inteligent, and high-function. Therefore, this paper is made a study for the method of energy saving and for energy saving of medium-small type small type-below 500kW medium type-between $500{\sim}1.000kW$.

• Journal of the Semiconductor & Display Technology
• /
• v.18 no.3
• /
• pp.42-46
• /
• 2019

In this paper, we introduce the novel idea to improve parallel test efficiency of semiconductor test. The idea includes the test interface card consisting of NoC structure able to transmitting test data regardless of ATE speed. We called the scheme "Multi-Clock" mode. In the proposed mode, because NoC can spread over the test data in various rates, many semiconductors are tested in the same time. We confirm the proposed idea will be promising through a FPGA board test and it is important to find a saturation point of the Multi-Clock mode due to the number of test chips and ATE channels.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.5 no.1
• /
• pp.1-6
• /
• 2010

본 논문에서는 네트워크 온 칩(NoC: network on chip) 구조에서의 내부 데이터 통신의 성능을 최적화 할 수 있는 새로운 온 칩 네트워크 인터페이스 구조를 제안하였다. 제안하는 NoC 구조는 기본적으로 하드웨어 면적을 줄이기 위하여 XY 라우팅 알고리듬을 기반으로 구현되었으며, 전달되는 패킷의 크기 또는 플릿의 개수를 최소화하기 위하여 Golomb-Rice 인코딩/디코딩 알고리듬에 기반을 둔 하드웨어 압축기/해제기를 이용하여 통신되는 데이터의 양을 크게 줄임으로써 네트워크 지연시간을 최소화 할 수 있는 새로운 구조를 제안하였다. 즉 전송될 데이터는 전송자(sender)의 네트워크 인터페이스에서 내장된 하드웨어 인코더를 통해 압축된 형태로 패킷의 개수를 최소화하여 온 칩 네트워크상의 데이터를 업로드하게 된다. 이러한 압축된 데이터가 리시버(receiver)에 도착하면, 하드웨어 디코더를 통해서 원래의 데이터로 복원된다. 사이클 수준의 시뮬레이터를 통하여 제안된 라우터 구조가 온 칩 시스템의 네트워크 지연시간을 크게 줄일 수 있음을 증명하였다.

• Proceedings of the Optical Society of Korea Conference
• /
• 2006.07a
• /
• pp.207-208
• /
• 2006

홈 네트워크를 구성하는 여러 분야 중 우리의 삶을 보다 풍요롭고 편리하게 하는, 멀티미디어와 관련된 홈 엔터테인먼트 분야가 강조되면서, 초고속 대용량 데이터의 원활한 전송이 요구되고 있다. 그러나 기존동선 가입자 선로는 이러한 요구를 수용하기에 그 한계에 다다르고 있다. 이로 인해 각 가정까지 광 가입자 선로가 직접 연결되는 FTTH(Fiber To The Home)에 대한 연구가 활발히 수행되고 있으며, 더 나아가 정보가전기기에 광 가입자 선로를 직접 연결하는 방식으로 그 관심이 확장되고 있다. 본 논문에서는 초고속 대용량 데이터의 전송을 위해 광 가입자 선로와 정보가전기기를 직접 연결시키는 방식에서 사용될 수 있는, 정보가전기기에 on-chip 시킬 수 있는 전/광(광/전) 변환 시스템을 설계하고 간략화하여 구현하였다.