• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.212-218
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• 2012

A stereo vision is able to build three-dimensional maps of its environment. It can provide much more complete information than a 2D image based vision but has to process, at least, that much more data. In the past decade, real-time stereo has become a reality. Some solutions are based on reconfigurable hardware and others rely on specialized hardware. However, they are designed for their own specific applications and are difficult to extend their functionalities. This paper describes a vision system based on a System on a Chip (SoC) platform. A real-time stereo image correlator is implemented using Sum of Absolute Difference (SAD) algorithm and is integrated into the vision system using AMBA bus protocol. Since the system is designed on a pre-verified platform it can be easily extended in its functionality increasing design productivity. Simulation results show that the vision system is suitable for various real-time applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.74-84
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• 2000

This paper deals with procedures for design and implementation of a DSP, which is compatible with TMS320C30 DSP. CBS(Cycle Based Simulator) is developed to study the architecture of the target DSP. The simulator gives us detailed information such as function block operation, control signal values, register condition, bus and memory values when a instruction is being carried out. RTL design is carried out by VHDL. Logic simulation and hardware emulation are employed to verify proper operation of the design. The DSP is fabricated with 0.6${\mu}m$ CMOS technology. The Chip has 450,000 gates complexity, $9{\times}9mm^2$ area, 20 MIPS operation speed. It is confirmed by running 109 instructions out of 114 instructions and 13 kinds of algorithm that the developed DSP has compatibility with TMS320C30.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.1 s.343
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• pp.121-126
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• 2006

This paper report on the design and implementation of a 9.6kbps DSSS CDMA modem for a medium speed wireless link. The proposed modem provides a general purpose I/O interface with a microprocessor. The I/O interface consists of 8-bit data bus, chip enable, read/write, and interrupt pins. In transmit block, the 8-bit data delivered from the I/O interface buffer is converted to 9.6kbps serial data, which are spreaded into 76.8kcps with 8-bit PN code generated inside the modem by direct sequence method. An 8-bit training sequence is preceded in the data frame for data synchronization in receiver. In receiver block the PN code is synchronized from the received data spreaded to 76.8kcps and find the data timing from the 8-bit training sequence. We have used the Early-and-Late integration method. The modem has been implemented and verified using a Xilix FPGA board and has been fabricated as an ASIC CHIP through Hynir $0.25{\mu}m$ CMOS. The multiple accessing method is DSSS CDMA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.126-133
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• 2006

This paper describes an AMBA-based IP to perform forward and inverse transform and quantization required in the H.264 video compression standard. The transform and quantization circuit was optimized for area and performance. The AHB wrapper was added to the circuit for the AMBA-based operation. The user of the IP can specify how long the bus may be occupied by the IP and also where the video data are stored in the external memory. The function of the proposed IP based on AMBA Specification was verified on the platform board with Xilinx FPGA and ARM9 processor. We fabricated an MPW chip using $0.25{\mu}m$ standard cells and observed its correct operations on silicon.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.1
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• pp.40-45
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• 2004

This paper presents the parallel distributed control scheme for shaping of the bent glass. The designed system consists of a PC, a main controller and 11 servo-controllers, the precision motion controllers. Each elements are connected by using RS-232C and 8-bit data bus. In order to guarantee the stability and the control performance, we use a precision PID motion controller and a H-bridge on the servo-drivers. PC calculates position values of 11 DC motors by using the pre-determined curvature value and offers the user interface environment operator. The main controller provides the control instructions and parameter values to 11 servo-controllers by chip enable signal, simultaneously. Using the received commands and parameter values, the servo-controllers control the positions of the DC motors based on PID control scheme.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.4
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• pp.356-361
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• 2008

The conventional drive system of SRM has a current sensor per each phase. The torque demand signal generated by the outer control loop is translated into individual current reference signal for each phase. The torque is controlled by regulating these currents. Using the SRM in a variable-speed control, the phase currents are generally regulated to achieve a square wave. The simplest form of current regulation uses fixed frequency delta modulation of the phase voltages. The aim of this paper is to regulate 3-phases current of SRM by only single current sensor using delta modulation with digital chip. In this paper, the asymmetric bridge converter which is able to control independently phases and be excited simultaneously is used as the driver system for 6/4 poles SRM. And the current sensor is replaced 3 sensors of each phase with only one on bus line of converter so as to detect current of every phase. The proposed delta modulation technique has been implemented in a simple digital logic circuit using EPLD(Electrically Programmable Logic Device). This method is verified through simulation and experiment results.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1959-1960
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• 2008

The Logic Built In Self Test (LBIST) technique is substantially applied in chip design in most many semiconductor company in despite of unavoidable overhead like an increase in dimension and time delay occurred as it used. Currently common LBIST software uses the MISR (Multiple Input Shift Register) However, it has many considerations like defining the X-value (Unknown Value), length and number of Scan Chain, Scan Chain and so on for analysis of result occurred in the process. So, to solve these problems, common LBIST software provides the solution method automated. Nevertheless, these problems haven't been solved automatically by Tri-state Bus in logic circuit yet. This paper studies the algorithm that it also suggest algorithm that reduce additional circuits and time delay as matching of pattern about 2-type circuits which are CUT(circuit Under Test) and additional circuits so that the designer can detect the wrong location in CUT: Circuit Under Test.

• Elastomers and Composites
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• v.56 no.1
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• pp.20-31
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• 2021

There is an increasing demand for the rolling resistance reduction in truck bus radial (TBR) tires in the tire industry. In TBR tires, natural rubber is used as a base polymer to prevent wear and satisfy required physical properties (cut and chip). A binary filler system (silica and carbon black) is used to balance the durability of the tire and rolling resistance performance. In this study, natural rubber (NR) compounds applied with a binary filler system were manufactured at different cure temperatures for vulcanizate structure analysis. The vulcanizate structures were categorized into carbon black bound rubber, silica silane rubber network, and chemical crosslink density by sulfur. Regardless of the cure temperature, the cross-link density per unit content of carbon black had a greater effect on the properties than silica due to affinity with NR. The relationship analysis between the mechanical, viscoelastic properties with vulcanizate structure could be a guideline for manufacturing practical TBR compounds.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.3
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• pp.699-707
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• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.9-17
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• 2006

We proposed a new High-speed CMOS Level Up/Down Shifter circuits that can be used with Dynamic Voltage and Frequency Scaling(DVFS) algorithm, for low power system in the SoC(System-on-Chip). This circuit used to interface between the other voltage levels in each CMOS circuit boundary, or between multiple core voltage levels in a system bus. Proposed circuit have advantage that decrease speed attenuation and duty ratio distortion problems for interface. The level up/down shifter of the proposed circuit designed that operated from multi core voltages$(0.6\sim1.6V)$ to used voltage level for each IP at the 500MHz input frequency The proposed circuit supports level up shifting from the input voltage levels, that are standard I/O voltages 1.8V, 2.5V, 3.3V, to multiple core voltage levels in between of $0.6V\sim1.6V$, that are used internally in the system. And level down shifter reverse operated at 1Ghz input frequency for same condition. Simulations results are shown to verify the proposed function by Hspice simulation, with $0.6V\sim1.6V$ CMOS Process, $0.13{\mu}m$ IBM CMOS Process and $0.65{\mu}m$ CMOS model parameters. Moreover, it is researched delay time, power dissipation and duty ration distortion of the output voltage witch is proportional to the operating frequency for the proposed circuit.