• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.1
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• pp.130-136
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• 2014

This paper reviews the research on silicon based phased array system operating from microwave to millimeter wave frequencies. First, the design of phase shifter using CMOS technology is presented. The passive phase shifter is applied to the transmit/receive module from one to 16 channel in a single chip. The 35 GHz 4-element T/R module consumes less than 200 mW both transmit and receive modes. The architecture can extend to 16-channel operating at 44 GHz, thereby improving transmit power and linearity. The Ku-band 2-antenna 4-element receiver was developed using active phase shifter based on vector sum method. It is important to minimize coupling between beams because the chip contains four independent beams. The method of coupling is presented and verified.

• Journal of the Korea Institute of Military Science and Technology
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• v.12 no.4
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• pp.446-451
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• 2009

In this paper, we described the design and test results of a high output power amplifier MMIC developed by using 0.5um power pHEMT processes on a 6-inch GaAs wafer for the X-band T/R module application. In the MMIC design, we have used a simple on-chip gate active bias technology to compensate the threshold-voltage variation of pHEMT during the fabrication process and 16-to-1 power combining method to achieve the output power over 10watt. The fabricated chip has an output power over 12watts and maximum PAE of 32% over the frequency range of fo +/-750MHz.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.75-79
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• 2013

A power distribution network (PDN) is a network that provides connection between the voltage source supply and the power/ground terminals of a microprocessor chip. It consists of a voltage regulator module, a printed circuit board, a package substrate, a microprocessor chip as well as decoupling capacitors. For power integrity analysis, the board and package layouts have to be transformed into an electrical network of resistor, inductor and capacitor components which may be expressed using the S-parameters models. This modeling process generally takes from several hours up to a few days for a complete board or package layout. When the board and package layouts change, they need to be re-extracted and the S-parameters models also need to be re-generated for power integrity assessment. This not only consumes a lot of resources such as time and manpower, the task of PDN modeling is also tedious and mundane. In this paper, a block-based PDN modeling is proposed. Here, the board or package layout is partitioned into sub-blocks and each of them is modeled independently. In the event of a change in power rails routing, only the affected sub-blocks will be reextracted and re-modeled. Simulation results show that the proposed block-based PDN modeling not only can save at least 75% of processing time but it can, at the same time, keep the modeling accuracy on par with the traditional PDN modeling methodology.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.149-154
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• 2018

This paper describes the fabrication and heat transfer property of 50 watts rated LED array module where multiple chips are mounted on chip-on-board type ceramic-metal hybrid substrate with high heat dissipation property for high power street and anti-explosive lighting system. The high heat transfer ceramic-metal hybrid substrate was fabricated by conformal coating of thick film glass-ceramic and silver pastes to form insulation and conductor layers, using thick film screen printing method on top of the high thermal conductivity aluminum alloy heat-spreading panel, then co-fired at $515^{\circ}C$. A comparative LED array module with the same configuration using epoxy resin based FR-4 PCB with thermalvia type was also fabricated, then the thermal properties were measured with multichannel temperature sensors and thermal resistance measuring system. As a result, the thermal resistance of the ceramic-metal hybrid substrate in the $4{\times}9$ type LEDs array module exhibited about one third to the value as that of FR-4 substrate, implying that at least triple performance of heat transfer property as that of FR-4 substrate was realized.

• Journal of Power Electronics
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• v.14 no.6
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• pp.1345-1356
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• 2014

The thermal behavior of power modules is an important criterion for the design of cooling systems and optimum thermal structure of these modules. An important consideration for high power and high frequency design is the spacing between semiconductor devices, substrate structure and influence of the boundary condition in the case. This study focuses on the thermal behavior of hybrid power modules to establish a simplified method that allows temperature estimation in different module components without decapsulation. This study resulted in a correction of the junction temperature values estimated from the transient thermal impedance of each component operating alone. The corrections depend on mutual thermal coupling between different chips of the hybrid structure. A new experimental technique for thermal mutual evaluation is presented. Notably, the classic analysis of thermal phenomena in these structures, which was independent of dissipated power magnitude and boundary conditions in the case, is incorrect.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.3
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• pp.1-7
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• 2021

In this paper, by embedding a bare-die chip-type drive amplifier into the PCB composed of ABF and FR-4, it implements an embedded active device that can be applied in 28 GHz band modules. The ABF has a dielectric constant of 3.2 and a dielectric loss of 0.016. The FR-4 where the drive amplifier is embedded has a dielectric constant of 3.5 and a dielectric loss of 0.02. The proposed embedded module is processed into two structures, and S-parameter properties are confirmed with measurements. The two process structures are an embedding structure of face-up and an embedding structure of face-down. The fabricated module is measured on a designed test board using Taconic's TLY-5A(dielectric constant : 2.17, dielectric loss : 0.0002). The PCB which embedded into the face-down expected better gain performance due to shorter interconnection-line from the RF pad of the Bear-die chip to the pattern of formed layer. But it is verified that the ground at the bottom of the bear-die chip is grounded Through via, resulting in an oscillation. On the other hand, the face-up structure has a stable gain characteristic of more than 10 dB from 25 GHz to 30 GHz, with a gain of 12.32 dB at the center frequency of 28 GHz. The output characteristics of module embedded into the face-up structure are measured using signal generator and spectrum analyzer. When the input power (P_in) of the signal generator was applied from -10 dBm to 20 dBm, the gain compression point (P_1dB) of the embedded module was 20.38 dB. Ultimately, the bare-die chip used in this paper was verified through measurement that the oscillation is improved according to the grounding methods when embedding in a PCB. Thus, the module embedded into the face-up structure will be able to be properly used for communication modules in millimeter wave bands.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.2
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• pp.119-127
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• 2008

In this paper, the modular line-connected photovoltaic PCS (photovoltaic power conditioning system) is proposed. A step-up DC-DC converter using a active-clamp circuit and a dual series-resonant rectifier is proposed to achieve a high efficiency and a high input-output voltage ratio efficiently. An IncCond (incremental conductance) MPPT (maximum power point tracking) algorithm that improves MPPT characteristic is used. The PV module current is estimated without using a DC current sensor. By control a inverter using a linearized output current controller, a unity power factor is achieved. All algorithms and controllers are implemented on a single-chip microcontroller and the superiority of the proposed DC-DC converter and controllers is proved by experiments.

• Journal of electromagnetic engineering and science
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• v.9 no.4
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• pp.188-193
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• 2009

A K-band low-power miniaturized planar-type hyperthermia system was developed to replace massive and expensive equipment. The system consists of a VCO with a buffer amplifier, a high-power amplifier module, a 20-dB-coupled line coupler, a chip circulator and two power detectors for signal generation, amplification and power monitoring. All these components have been implemented in planar form on two module blocks. The total size of the hyperthermia system was less than $10\times6.5\times3\;cm^3$. In order to verify the system performance, ablations were carried out on nude mice xenografted with human breast cancer. Ablation results show performance comparable to the massive components-based system. This work shows the feasibility of a low-cost miniaturized hyperthermia system for practical clinical applications.

• Journal of Information Processing Systems
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• v.5 no.4
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• pp.187-196
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• 2009

This paper presents compact cryptographic hardware architecture suitable for the Mobile Trusted Module (MTM) that requires low-area and low-power characteristics. The built-in cryptographic engine in the MTM is one of the most important circuit blocks and contributes to the performance of the whole platform because it is used as the key primitive supporting digital signature, platform integrity and command authentication. Unlike personal computers, mobile platforms have very stringent limitations with respect to available power, physical circuit area, and cost. Therefore special architecture and design methods for a compact cryptographic hardware module are required. The proposed cryptographic hardware has a chip area of 38K gates for RSA and 12.4K gates for unified SHA-1 and SHA-256 respectively on a 0.25um CMOS process. The current consumption of the proposed cryptographic hardware consumes at most 3.96mA for RSA and 2.16mA for SHA computations under the 25MHz.