• Science of Emotion and Sensibility
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• v.13 no.1
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• pp.235-242
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• 2010

Emotion science is one of the rapidly expanding engineering/scientific disciplines which has a major impact on human society. Such growing interests in emotion science and engineering owe the recent trend that various academic fields are being merged. In this paper we review the recent techniques in the measuring the emotion related elements and applications which include animal model system to investigate the neural network and behaviour, artificial nose/neuronal chip for in-depth understanding of sensing the outer stimuli, metabolic controlling using emotional stimulant such as sounds. In particular, microfabrication techniques made it possible to construct nano/micron scale sensing parts/chips to accommodate the olfactory cells and neuron cells and gave us a new opportunities to investigate the emotion precisely. Recent developments in the measurement techniques will be able to help combine the social sciences and natural sciences, and consequently expand the scope of studies.

• Korean Journal of Remote Sensing
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• v.36 no.5_2
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• pp.881-891
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• 2020

Recently, the Ministry of Land, Infrastructure and Transport and the Ministry of Science and ICT are developing the Land Observation Satellite (CAS-500) to meet increased demand for high-resolution satellite images. Expected image products of CAS-500 includes precision orthoimage, Digital Surface Model (DSM), change detection map, etc. The quality of these products is determined based on the geometric accuracy of satellite images. Therefore, it is important to make precision geometric corrections of CAS-500 images to produce high-quality products. Geometric correction requires the Ground Control Point (GCP), which is usually extracted manually using orthoimages and digital map. This requires a lot of time to acquire GCPs. Therefore, it is necessary to automatically extract GCPs and reduce the time required for GCP extraction and orthoimage generation. To this end, the Precision Image Processing (PIP) System was developed for CAS-500 images to minimize user intervention in GCP extraction. This paper explains the products, processing steps and the function modules and Database of the PIP System. The performance of the System in terms of processing speed, is also presented. It is expected that through the developed System, precise orthoimages can be generated from all CAS-500 images over the Korean peninsula promptly. As future studies, we need to extend the System to handle automated orthoimage generation for overseas regions.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.50-50
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• 1999

마이크로 공정을 이용한 초소형 정밀 기계는 공정 기술과 재료 기술의 발전에 의하여 더욱 소형화되고 있으며 특히 기능을 갖는 부분과 이 부분을 제어하는 주변회로의 on-chip화의 요구가 증가되기 시작하였다. 이와 같은 추세에 있어서의 문제점은 초소형 정밀기계 부품 소자의 구동을 위한 에너지원의 개발이다. 즉, 소자의 크기가 작아진 것에 부합되는 초소형의 전지가 필요하게 된 것이다. 따라서 보다 완전한 초소형 정밀 기계 및 마이크로 소자의 구현을 위하여 마이크로 소자와 혼성 (Hybrid) 되어 이용될 수 있는 고성능 및 초소형의 전지의 개발이 필수적이다. 초소형 전지의 구현을 위하여 Li계의 2차 전지를 선택하여 이를 박막화하고 반도체 공정을 도입할 수 있다. 이러한 전지를 박막형 2차 전지 또는 박막형 마이크로 전지(thin film Secondary Battery : TFSB or Thin Film Micro-Battery : TFMB)라 하며 이러한 2차 전지는 일반적인 벌크 전지와 동일하게 cathode/Electolyte/Anode의 구조를 갖는다. 박막의 특성상 전해질은 고상의 물질을 사용하는 것이 벌크형 2차 전지와 다른 점이다. TFSB의 성능은 주로 cathode에 의하여 결정되며 지금까지 많은 cathode 물질에 대한 연구 보고가 발표되고 있다. 반도체 공정을 이용한 TFMB의 제작시 무엇보다 중요한 점은 우수한 고상 전해질 및 anode 물질의 선택에 있다. 최근에 2차 전지를 위한 carbon계 anode를 대체할 수 있는 SnO에 대한 보고가 있는데 이는 한 개의 Sn 원자당 2개 이사의 Li가 반응하여 높은 용량을 갖는 전지의 제작이 가능하기 때문이다. Sno2의 anode는 매우 높은 충전용량을 갖는데 첫 번째 방전시에 Li2O를 생성하여 비가역적 반응을 나타내고 계속되는 충방전 동안 Li-Sn 합금이 생성되어 2차전지의 가역적 반응을 가능하게 한다. SnO2 는 대기중에서 Li 금속보다 안정하기 때문에 전지의 제작 공정 및 사용 면에서 매우 우수한 물질이지만 아직까지 SnO2 구조적 특성과 전지의 충, 방전 특성에 대한 관계의 규명을 위한 정확한 정설은 제시되고 있지 못하다. 본 연구에서는 TFSB anode 물질로써 SnOx박막을 상온에서 여러 전도성 콜렉터 위에 증착하여 그 충, 방전 특성을 보고하였다. 증착된 SnOx박막의 표면은 SEM, AFM으로 분석하였으며 구조의 분석은 XR와 Auger electron spectroscope로 하였다. 충, 방전 특성을 분석하기 위하여 리늄 foil을 대극과 참조 전극으로 하여 EC:DMC=1:1, 1M LiPF6 액체 전해질을 사용한 Half-Cell를 구성하여 100회 이상의 정전류 충, 방전 시험을 행하였다. Half-Cell test 결과 박막의 구조, 콜렉터의 종류 및 Sn/O비에 따라 서로 다른 충, 방전 거동을 나타내었다.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.4
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• pp.11-15
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• 2001

In this paper, hermetic sealing technology was studied for wafer level packaging of the RF-MEMS devices. With the flip-chip bonding method. this non-conductive B-stage epoxy sealing will be profit to the MEMS device sealing. It will be particularly profit to the RF-MEMS device sealing. B-stage epoxy can be cured by 2-step and hermetic sealing can be obtained. After defining 500 $\mu\textrm{m}$-width seal-lines on the glass cap substrate by screen printing, it was pre-baked at $90^{\circ}C$ for about 30 minutes. It was, then, aligned and bonded with device substrate followed by post-baked at $175^{\circ}C$ for about 30 minutes. By using this 2-step baking characteristic, the width and the height of the seal-line could be maintained during the sealing process. The height of the seal-line was controlled within $\pm$0.6 $\mu\textrm{m}$ in the 4 inches wafer and the bonding strength was measured to about 20MPa by pull test. The leak rate, that is sealing characteristic of the B-stage epoxy, was about $10^{-7}$ cc/sec from the leak test.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.17-26
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• 2010

Pb-Sn solder is rapidly being replaced by lead-free solder for board-level interconnection in microelectronic package assemblies due to the environmental protection requirement. There is a general lack of mechanical reliability information available on the lead-free solder. In this study, thermo-mechanical behaviors of wire-bond plastic ball grid array (WB-PBGA) package assemblies are characterized by high-sensitivity moire interferometry. Experiments are conducted for two types of WB-PBGA packages that have Pb-Sn solder and lead-free solder as joint interconnections. Using real-time moire setup, fringe patterns are recorded and analyzed for several temperatures. Bending deformations of the assemblies and average strains of the solder balls are investigated and compared for the two type of WB-PBGA package assemblies. Results show that shear strain in #3 solder ball located near the chip shadow boundary is dominant for the failure of the package with Pb-Sn solder, while normal strain in #7 most outer solder ball is dominant for that with lead-free solder. It is also shown that the package with lead-free solder has much larger bending deformation and 10% larger maximum effective strain than the package with Pb-Sn solder at same temperature level.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.187-187
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF($2^8$) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.1-8
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• 2005

In this paper, CMOS A/D converter with 6bit 2GSPS Nyquist input at 1.8V is designed. In order to obtain the resolution of 6bit and the character of high-speed operation, we present an Interpolation type architecture. In order to overcome the problems of high speed operation, a novel One-zero Detecting Encoder, a circuit to reduce the Reference Fluctuation, an Averaging Resistor and a Track & Hold, a novel Buffered Reference for the improved SNR are proposed. The proposed ADC is based on 0.18um 1-poly 3-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply and occupies chip area of 977um $\times$ 1040um. Experimental result show that SNDR is 36.25 dB when sampling frequency is 2GHz and INL/DNL is $\pm$0.5LSB at static performance.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.29-38
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF(2$^{8}$ ) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.28-34
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• 2010

In this paper, the transceiver for RFID reader using 13.56MHz as a carrier frequency and meeting International Standard ISO 14443 type A, 14443 type B and 15693 is presented. The receiver is composed of envelope detector, VGA(Variable Gain Amplifier), filter, comparator to recovery the received signal. The proposed automatic reference voltage generator, positive peak detector, negative peak detector, and data slicer circuit can adjust the decision level of reference voltage over the received signal amplitudes. The transmitter is designed to drive high voltage and current to meet the 15693 specification. By using inductor loading circuit which can swing more than power supply and drive large current even under low impedance condition, it can control modulation rate from 30 percent to 5 percent, 100 perccnt and drive the output currents from 5 mA to 240 mA depending on standards. The 13.56 MHZ RFID reader is implemented in $0.18\;{\mu}m$ CM08 technology at 3.3V single supply. The chip area excluding pads is $1.5mm\;{\times}\;1.5mm$.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.68-73
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• 2013

In this paper, we proposed a readout circuit of pulse waveform and rate for a U-health system to monitor health condition. For long-time operation without replacing or charging a battery, either pulse waveform or pulse rate is selected as the output data of the proposed readout circuit according to health condition of a user. The proposed readout circuit consists of a simple digital logic discriminator and a dual-mode ADC which operates in the ADC mode or in the count mode. Firstly, the readout circuit counts pulse rate for 4 seconds in the count mode using the dual-mode ADC. Health condition is examined after the counted pulse rate is accumulated for 1 minute in the discriminator. If the pulse rate is out of the preset normal range, the dual-mode ADC operates in the ADC mode where pulse waveform is converted into 10-bit digital data with the sampling frequency of 1 kHz. These data are stored in a buffer and transmitted by 620 kbps to an external monitor through a RF transmitter. The data transmission period of the RF transmitter depends on the operation mode. It is generally 1 minute in the normal situation or 1 ms in the emergency situation. The proposed readout circuit was designed with $0.11{\mu}m$ process technology. The chip area is $460{\times}800{\mu}m^2$. According to measurement, the power consumption is $161.8{\mu}W$ in the count mode and $507.3{\mu}W$ in the ADC mode with the operating voltage of 1 V.