• Journal of the Korean Society of Industry Convergence
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• v.15 no.2
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• pp.55-58
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• 2012

This study is concerned about the design and structural analysis of high integrated Chip Bonding Machine. Recently, many studies have been undergoing to reduce a working time in a field of Chip Bonding Machine. Chip Bonding Machine belongs to reduce a stand-by time by Chip Moving time. The developed system can save tool moving distance in small space than other machine. The analysis is carried out by SoldEdge & Ansys software.

• Proceedings of the KWS Conference
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• 2007.11a
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• pp.218-221
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• 2007

The surface mounting technology of 0402 electric chip part is necessary to fabricate a high density and multi-functional module, but there is a limitation of the technology, like as a bridge and self-alignement. This work estimated SMT processing factors of 0402 chip. To obtain optimum SMT process, we evaluated effects of stencil thickness, shape of hole on printability and mountability. Printability shows best results under the thickness of $80{mu}m$ with circle hole shape and 90% square hole shape. In case of chip mounting process, chip mis-alignment and bridge was occurred rarely in same conditions. In more thin stencil thickness, $50{mu}m$, strength of 1005 chip parts was poor, because of amount of printed solder was insufficient.

• Electronics and Telecommunications Trends
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• v.36 no.3
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• pp.1-11
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• 2021

In this study, we analyze the automotive chip ecosystem that recently caused the global supply shortage, and attempt to derive policy implications for us from the conclusion. Automotive chips are critical parts that control various systems so that a vehicle can drive itself or operate with electricity. The current shortage in supply and demand for automotive chips is due to the inconsistency between supply and demand between automotive chip companies and car manufacturers. To promote the automotive chip industry, new investment incentives, tax cuts, and human resource training are needed.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.4
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• pp.1-10
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• 2020

This paper reviews the recent development of electronic textile technology, mainly focusing on chip-textile bonding. Before the chip-textile bonding, a circuit on the textile should be prepared to supply the electrical power and signal to the chip mounted on the fabrics. Either embroidery with conductive yarn or screen-printing with the conductive paste can be applied to implement the circuit on the fabrics depending on the circuit density and resolution. Next, chip-textile bonding can be performed. There are two choices for chip-textile bonding: fixed connection methods such as soldering, ACF/NCA, embroidery, crimping, and secondly removable connection methods like a hook, magnet, zipper. Following the chip-textile bonding process, the chip on the textile is generally encapsulated using PDMS to ensure reliability like water-proof.

• Animal cells and systems
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• v.14 no.1
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• pp.1-10
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• 2010

Previously we showed that CHIP, a co-chaperone of Hsp70 and E3 ubiquitin ligase, can promote the degradation of mutant SOD1 linked to familial amyotrophic lateral sclerosis (fALS) via a mechanism not involving SOD1 ubiquitylation. Here we present evidence that CHIP functions in the interaction of mutant SOD1 with 26S proteasomes. Bag-1, a coupling factor between molecular chaperones and the proteasomes, formed a complex with SOD1 in an hsp70-dependent manner but had no direct effect on the degradation of mutant SOD1. Instead, Bag-1 stimulated interaction between CHIP and the proteasome-associated protein VCP (p97), which do not associate normally. Over-expressed CHIP interfered with the association between mutant SOD1 and VCP. Conversely, the binding of CHIP to mutant SOD1 was inhibited by VCP, implying that the chaperone complex and proteolytic machinery are competing for the common substrates. Finally we observed that mutant SOD1 strongly associated with the 19S complex of proteasomes and CHIP over-expression specifically reduced the interaction between S6/S6' ATPase subunits and mutant SOD1. These results suggest that CHIP, together with ubiquitin-binding proteins such as Bag-1 and VCP, promotes the degradation of mutant SOD1 by facilitating its translocation from ATPase subunits of 19S complex to the 20S core particle.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.376-379
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• 2001

In this paper, I design the control chip that controls inner test sequence of Logic Tester to test chip. Logic tester has the thirteen inner instructions to control test sequence in test. And these instructions are saved in memory with test pattern data. Control chip generates address and control signal such as read, write signal of memory. Before testing, necessary data such as start address, end address, etc. are written to inner register of control chip. When test started, control chip receives the instruction in start address and executes, and generates address and control signals to access tester' inner memory. So whole test sequence is controlled by making the address and control signal in tester's inner memory. Control chip designs instruction's execution blocks, respectively. So if inner instruction is added from now on, a revision is easy. The control chip will be made using FPGA of Xilinx Co. in future.

• Journal of information and communication convergence engineering
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• v.6 no.2
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• pp.122-128
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• 2008

Multiprocessor architectures and platforms, such as, a multiprocessor system on chip (MPSoC) recently introduced to extend the applicability of the Moore's law, depend upon concurrency and synchronization in both software and hardware to enhance design productivity and system performance. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and non-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future System-on-Chip (SoC). We have modeled a concurrent architecture for a customizable and scalable NOC in a system level modeling environment using MLDesigner (from MLD Inc.). Varying network loads under various traffic scenarios were applied to obtain realistic performance metrics. We provide the simulation results for latency as a function of the buffer size. We have abstracted the area results for NOC components from its FPGA implementation. Modeled NOC architecture supports three different levels of quality-of-service (QoS).

• Journal of the Korean Institute of Intelligent Systems
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• v.10 no.3
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• pp.270-279
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• 2000

This paper describes the on-chip learning algorithm of neural networks using the stochastic pulse arithmetic. Stochastic pulse arithmetic is the computation using the numbers represented by the probability of 1' and 0's occurrences in a random pulse stream. This stochastic arithmetic has the merits when applied to neural network ; reduction of the area of the implemented hardware and getting a global solution escaping from local minima by virtue of the stochastic characteristics. And in this study, the on-chip learning algorithm is derived from the backpropagation algorithm for effective hardware implementation. We simulate the nonlinear separation problem of the some character patterns to verify the proposed learning algorithm. We also had good results after applying this algorithm to recognize printed and handwritten numbers.

• ETRI Journal
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• v.33 no.3
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• pp.335-343
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• 2011

The pad pitch of modern radio frequency integrated circuits is in the order of few tens of micrometers. Connecting a large number of high-speed I/Os to the outside world with good signal fidelity at low cost is an extremely challenging task. To cope with this requirement, we need reflection-free transmission lines from an on-chip pad to on-board SMA connectors. Such a transmission line is very hard to design due to the difference in on-chip and on-board feature size and the requirement for extremely large bandwidth. In this paper, we propose the use of narrow tracks close to chip and wide tracks away from the chip. This narrow-to-wide transition in width results in impedance discontinuity. A step change in substrate thickness is utilized to cancel the effect of the width discontinuity, thus achieving a reflection-free microstrip. To verify the concept, several microstrips were designed on multilayer FR4 PCB without any additional manufacturing steps. The TDR measurements reveal that the impedance variation is less than 3 ${\Omega}$ for a 50 ${\Omega}$ microstrip and S11 better than -9 dB for the frequency range 1 GHz to 6 GHz when the width changes from 165 ${\mu}m$ to 940 ${\mu}m$, and substrate thickness changes from 100 ${\mu}m$ to 500 ${\mu}m$.

• KIEE International Transactions on Electrophysics and Applications
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• v.4C no.4
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• pp.133-136
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• 2004

This research aims to develop a DNA chip array without an indicator. We fabricated a microelectrode array through photolithography technology. Several DNA probes were immobilized on an electrode. Then, target DNA was hybridized and measured electrochemically. Cyclic-voltammograms (CVs) showed a difference between the DNA probe and mismatched DNA in an anodic peak. This indicator-free DNA chip resulted in a sequence-specific detection of the target DNA.