• Journal of the KSME
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• v.50 no.1
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• pp.37-41
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• 2010

최근 미세유체기술(microfluidics)을 기반으로 한 lab on a chip 기술이 기계, 의료, 바이오, 제약, 화학, 환경 분야 등의 다양한 분야에서 각광 받고 있다. 이 글에서는 일회용 고분자 lab on a chip 대량생산의 기반 기술에 해당하는 고분자 미세성형 기술에 대해 소개한다.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.11a
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• pp.387-388
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• 2010

• Biotechnology and Bioprocess Engineering:BBE
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• v.9 no.2
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• pp.100-106
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• 2004

Micro-fluidics is one of the major technologies used in developing micro-total analytical systems (${\mu}$-TAS), also known as “lab-on-a-chip”. With this technology, the analytical capabilities of room-size laboratories can be put on one small chip. In this paper, we will briefly introduce materials that can be used in micro-fluidic systems and a few modules (mixer, chamber, and sample prep. modules) for lab-on-a-chip to analyze biological samples. This is because a variety of fields have to be combined with micro-fluidic technologies in order to realize lab-on-a-chip.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.2
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• pp.201-206
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• 2007

In this paper, we propose the efficient low power test methodology of NoC(Network-on chip) for the test of core-based systems that use this platform. To reduce the power consumption of transferring data through router channel, the scan vectors are partitioned into flits by channel width. The don't cares in unspecified scan vectors are mapped to binary values to minimize the switching rate between flits. Experimental results for full-scanned versions of ISCAS 89 benchmark circuits show that the proposed method leads to about 35% reduction in test power.

• Journal of IKEEE
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• v.16 no.4
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• pp.405-409
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• 2012

In this paper, on-chip antennas applicable to ultra low power wireless transceiver are designed and evaluated. Using $0.18{\mu}m$ SiGe MMIC process, 4 types of antenna with $1{\times}1mm^2$ dimensions are fabricated. The on-wafer measurement in a microwave probe station is conducted to measure the input VSWR and antenna performance of the designed on-chip antenna. Performance evaluation results show that developed antennas can be easily integrated into one-chip RF transceiver for ubiquitous applications, including WPAN and human body communications.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.21-26
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• 2002

Solder flip chip bumping and subsequent coining processes on PCB were investigated to solve the warpage problem of organic substrates for high pin count flip chip assembly by providing good co-planarity. Coining of solder bumps on PCB has been successfully demonstrated using a modified tension/compression tester with height, coining rate and coining temperature variables. It was observed that applied loads as a function of coined height showed three stages as coining deformation : (1) elastic deformation at early stage, (2) linear increase of applied load, and (3) rapid increase of applied load. In order to reduce applied loads for coining solder bumps on PCB, effects of coining process parameters were investigated. Coining loads for solder bump deformation strongly depended on coining rates and coining temperatures. As coining rates decreased and process temperature increased, coining loads decreased. Among the effect of two factors on coining loads, it was found that process temperature had more significant effect to reduce applied coining loads during the coining process. Lower coining loads were needed to prevent substrate damages such as micro-via failure and build-up dielectric layer thickness change during applying loads. For flip chip assembly, 97Pb/Sn flip chip bumped devices were successfully assembled on organic substrates with 37Pb/Sn coined flip chip bumps.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2002.10b
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• pp.319-320
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• 2002

Numerical simulation of chip formation during high speed machining requires knowing the friction at tool/chip interface. This parameter is hardly identified and generally the loadings (temperature, force) during the identification are not similar to those encountered during machining. Thus, Coulomb friction identified with pin-on-disc device is often used to conduct numerical simulation. The used of this technique cannot leads to good numerical results of chip formation compared to the experimental tests especially in the case of low uncut chip thickness. In this contribution, we propose a new method to evaluate the friction at tool/chip interface. In fact several Coulomb friction parameters are identified corresponding to several parts of the cutting tool. Experimental tests have been conducted allowed us to determinate both the level and the distribution of the Coulomb friction. Experimental results are also compared to the results of orthogonal cutting simulation. We show that this technique allows predicting accuracy results of chip formation.

• ETRI Journal
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• v.32 no.6
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• pp.969-971
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• 2010

Based on a de-embedding technique, a new method is proposed which is capable of evaluating chip impedance behavior over absorbed power in flip-chip bonded UHF radio frequency identification transponder ICs. For the de-embedding, four compact co-planar test fixtures, an equivalent circuit for the fixtures, and a parameter extraction procedure for the circuit are developed. The fixtures are designed such that the chip can absorb as much power as possible from a power source without radiating appreciable power. Experimental results show that the proposed modeling method is accurate and produces reliable chip impedance values related with absorbed power.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.4
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• pp.160-164
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• 2004

In DS/CDMA(direct sequence code division multiple access) system using the approximated analytic chip waveforms are applied. Proposed chip waveforms are classified into 2 types: uniform chip waveforms with uniform envelope and non-uniform chip waveforms with non-uniform envelope. It has confirmed that the similarity of the approximated analytical chip waveforms is compared using chip waveforms, envelope, phase, correlation, and bandwidth properties.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.1109-1112
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• 1999

본 논문에서는 영상확대 chip의 video 입력부에 부분화면을 저장할 frame memory의 구조를 개선하고자 하였다. 영상확대 video scaler인 gm833×2는 입력단 측에 frame buffer memory가 필요하게 되지만, 이를 외부에 장착하려면 일반적으로 대용량의 FIFO 메모리를 사용하게 된다. 이것은 dualport SRAM으로 구성이 되며, 메모리 제어를 고가의 FIFO칩에 의존하는 결과를 가져온다. 또한 기존의 scaler chip은 단순히 확대처리만을 하며, 입력 전, 후에 data의 변경 또는 이미지처리가 불가능한 구조가 된다. 본 논문에서는 외부에 필요한 메모리를 내장한 새로운 기능의 chip을 설계하는 데에 있어 필수적인 메모리제어 로직을 제안하고자 한다. 여기서는 더 나은 기능의 향상된 메모리 제어회로를 제시하고 이를 One-chip에 집적할 수 있도록 하였다 이를 사용한 Video Scaler Processor chip은 SDRAM을 별도의 제어회로 없이 외부에 장착할 수 있도록 하여 scaler의 기능을 향상시키면서 전체 시스템의 구조를 간단히 할 수 있을 것으로 기대된다. 본 논문에서는 먼저 메모리 제어회로를 포함한 Video Scaler Processor chip의 메모리제어 하드웨어의 구조를 제시하고, 메모리 access model과 제어로직을 소개하고자 한다.