• Journal of Sensor Science and Technology
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• v.26 no.5
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• pp.331-337
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• 2017

A readout circuit for a tactile sensor pad based on force sensing resistors was proposed, which was composed of an analog signal conditioning circuit and a digital circuit with a microcontroller. The conventional signal conditioning circuit has a dc offset voltage in the output signal, which results from the reference voltage applied to the FSR devices. The offset voltage reduces the dynamic range of the circuit and makes it difficult to operate the circuit under a low voltage power supply. In the proposed signal conditioning circuit, the dc offset voltage was removed completely. The microcontroller with A/D converter and D/A converter was used to enlarge the measurement range of pressure. For this, the microcontroller adjusts the FSR reference voltage according to the resistance magnitude of FSR under pressure. The operation of the proposed readout circuit which was connected to a tactile sensor pad with $5{\times}10$ FSR array was verified experimentally. The experimental results show the proposed readout circuit has the wider measurement range of pressure than the conventional circuit. The proposed circuit is suitable for low voltage and low power applications.

• International Journal of Internet, Broadcasting and Communication
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• v.15 no.3
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• pp.122-128
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• 2023

This paper proposes two kinds of single-balanced direct conversion quadrature receivers using selfoscillating LMVs in which the voltage-controlled oscillator (VCO) itself operates as a mixer while generating an oscillation. The two LMVs are complementary coupled and series coupled to generate the quadrature oscillating signals, respectively. Using a 65 nm CMOS technology, the proposed quadrature receivers are designed and simulated. Oscillating at around 2.4 GHz frequency, the complementary coupled quadrature receiver achieves the phase noise of -28 dBc/Hz at 1KHz offset and -109 dBc/Hz at 1 MHz offset frequency. The other series coupled receiver achieves the phase noise of -31 dBc/Hz at 1KHz offset and -109 dBc/Hz at 1 MHz offset frequency. The simulated voltage conversion gain of the two single-balanced receivers is 37 dB and 45 dB, respectively. The double-sideband noise figure of the two receivers is 5.3 dB at 1 MHz offset. The quadrature receivers consume about 440 μW dc power from a 1.0-V supply.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.11
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• pp.68-76
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• 2014

This paper presents an offset error compensation algorithm for the accurate phase angle of the grid voltage in single-phase grid-connected inverters. The offset error generated from the grid voltage measurement process cause the fundamental harmonic component with grid frequency in the synchronous reference frame phase lock loop (PLL). As a result, the grid angle is distorted and the power quality in power systems is degraded. In addition, the dq-axis currents in the synchronous reference frame and phase current have the dc component, first and second order ripples compared with the grid frequency under the distorted grid angle. In this paper, the effects of the offset and scaling errors are analyzed based on the synchronous reference frame PLL. Particularly, the offset error can be estimated from the integrator output of the synchronous reference frame PLL and compensated by using proportional-integral controller. Moreover, the RMS (Root Mean Square) function is proposed to detect the offset error component. The effectiveness of the proposed algorithm is verified through simulation and experiment results.

• Journal of Electrical Engineering and Technology
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• v.10 no.1
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• pp.138-145
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• 2015

In this paper, a novel static overmodulation scheme (OVM) for space-vector PWM (SVPWM) is proposed. The proposed static OVM scheme uses the concept of adding offset voltages in linear region as well as overmodulation region to fully utilize DC-link voltage. By employing zero sequence voltage injection, the proposed scheme reduces procedures for achieving SVPWM such as complicated gating time calculation. In addition, this paper proposes a stepwise discontinuous angle movement in high modulation region in order to reduce Total Harmonic Distortion (THD). The validity of the proposed scheme is verified through theoretical analysis and experimental results.

• Journal of Industrial Technology
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• v.22 no.B
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• pp.133-139
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• 2002

In precision instrumentation system, an A/D conversion of signal conditioning has been always suffered from some problems ; offset and drift voltage with environmental situation. This paper suggests a method of reducing the offset voltage and the drift error from the A/D conversion hardware using analog signal switching technique with specific operational amplifier circuits. Also, we have designed a hardware active filter and a software digital filter with Auto Zero Tracking algorithm for better dignal process of the our proposed weighing system. Software technique was performed to obtain the stable data from A/D converter. As a result of our experimental works, the proposed system is expected to be used in the industrial field where a high precision measurement is required.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.268-272
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• 2001

In this thesis, PLVCO(Phase Locked Voltage Controlled Oscillator) using 24.42 GHz voltage controlled hair-pin resonator oscillator, Sequency divider, buffer amplifier, -10 dB directional coupler and phase detector is designed and fabricated for B-WLL. The PLVCO shows the oscillator output power of 16.5 dBm at 24.42 GHz, and phase noise of -76.3 dBc/Hz at 1001:Hz offset, -72.8dBc/Hz at 10 kHz offset from fundamental frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.18-27
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• 2010

In this paper, a 1.2V 7-bit 1GSPS A/D converter with offset self-calibration is proposed. The proposed A/D converter structure is based on the folding-interpolation whose folding rate is 2, interpolation rate is 8. Further, for the purpose of improving the chip performance, an offset self-calibration circuit is used. The offset self-calibration circuit reduce the variation of the offset-voltage，due to process mismatch, parasitic resistor, and parasitic capacitance. The chip has been fabricated with a 1.2V 65nm 1-poly 6-metal CMOS technology. The effective chip area is $0.87mm^2$ and the power dissipates about 110mW at 1.2V power supply. The measured SNDR is about 39.1dB when the input frequency is 250MHz at 800MHz sampling frequency. The measured SNDR is 3dB higher than the same circuit without any calibration.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.26-29
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• 1999

The I-V characteristics of the n-channel offset gated poly-Si TETs have been systematically investigated in order to analyse the effects of offset region. The on currents are reduced due to the series resistance by the offset length and there is no kink phenomenon in offset devices. The off currents of the offset gated TFTs are remarkably reduced to 10$^{-12}$ A independent of gate and drain voltage because the electric field is weakened by the increase of the depletion region width near the drain region. It is shown that the offset regions behave as a series resistance and reduce lateral and vertical electric field.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.1
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• pp.68-71
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• 2020

As a T-type three-level PWM converter has several intrinsic advantages, it has been widely studied for many applications. However, it requires an additional voltage control loop for balancing each DC link voltage. Generally, satisfying this requirement involves the use of an offset voltage to provide a neutral point current without affecting other variables, such as the total DC link voltage and three-phase input current. In this study, the theoretical relationship between the offset voltage and the neutral point current is analyzed. The results can be beneficial for effective voltage balancing controller design. The effectiveness of the analytical modeling is verified by simulation and experimental results.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2007.04a
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• pp.477-480
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• 2007

저전력 OFDM(orthogonal frequency division multiplexing) 시스템용 FFT(Fast-Fourier-Transform) LSI를 저전력 동작을 시키기 위해서 FFT LSI는 current-mode 회로로 구현되었다. Current-mode FFT LSI에서, VIC(Voltage-to-current converter)는 입력 전압 신호를 전류로 바꾸는 first main device이다. 저전력 OFDM을 위해 FFT LSI와 VIC가 한 개의 칩과 결합되는 것을 고려하면, VIC는 전력 손실은 낮고, VIC와 FFT LSI 사이에서의 DC offset 전류는 최소인 작은 크기의 chip으로 설계되어야 한다. 본 논문에서는 새로운 VIC를 제안한다. 선형 동작구간을 넓히고 DC offset 전류를 대폭 감소하는 방법을 제시하였다. VIC는 0.35[um] CMOS process로 구현되었으며, 시뮬레이션 결과에 따르면 제안된 VIC는 current-mode FFT LSI와 0.1[uA] 미만의 매우 작은 DC offset 전류, 1.4[V]의 넓은 선형구간을 갖으며, 저전력으로 동작한다.