• Journal of Power Electronics
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• 제15권2호
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• pp.504-517
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• 2015

This paper presents a novel switching voltage model and an offset-based pulse width modulation (PWM) scheme for multilevel inverters with unbalanced DC sources. The switching voltage model under a DC voltage imbalance will be formulated in general form for multilevel neutral-point-clamped topologies. Analysis of the reference switching voltages from active and non-active switching voltage components in abc coordinates can enable voltage implementation for an unbalanced DC-source condition. Offset voltage is introduced as an indispensable variable in the switching voltage model for multilevel voltage-source inverters. The PWM performance is controlled through the design of two offset components in a subsequence. One main offset may refer to the common mode voltage, and the other offset restricts its effect on the quality of PWM control in related DC levels. The PWM quality can be improved as the switching loss is reduced in a discontinuous PWM mode by setting the local offset, which is related to the load currents. The validity of the proposed algorithm is verified by experimental results.

• 전기학회논문지
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• 제64권7호
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• pp.1005-1011
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• 2015

This paper proposes the DC offset compensation algorithm with fast response to the sensed grid voltage in the single-phase grid connected inverter. If the sensor of the grid voltage has problems, the DC offset of the grid voltage can be generated. This error must be resolved because the DC offset can generate the estimated grid frequency error of the phase-locked loop (PLL). In conventional algorithm to compensate the DC offset, the DC offset is estimated by integrating the synchronous reference frame d-axis voltage during one period of the grid voltage. The conventional algorithm has a drawback that is a slow dynamic response because monitoring the one period of the grid voltage is required. the proposed algorithm has fast dynamic response because the DC offset is consecutively estimated by transforming the d-axis voltage to synchronous reference frame without monitoring one cycle time of the grid voltage. The proposed algorithm is verified from PSIM simulation and the experiment.

• 전자공학회논문지A
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• 제29A권7호
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• pp.82-88
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• 1992

This paper presents one of the first comprehensive studies of how hot electron degradation impacts the input offset voltage of a CMOS differential amplifiers. This study utilizes the concept of a virtual source-coupled MOSFET pair in order to evaluate offset voltaged egradation directly from individual device measurement. Next, analytical models are developed to describe the offset voltage degradation. These models are used to examine how hot electron induced offset voltage is affected with the device parameters.

• 전자공학회논문지A
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• 제32A권1호
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• pp.138-145
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• 1995

The offset voltage in silicon Hall plates is mainly caused by stress and strain in package, and by alignment in process. The offset voltage is appeared random for condition change with time in the factory, is non-linearly changed with temperature. In this paper proposed new method of design of Hall IC, and methematicaly proved relation layout of chip of 90$^{\circ}$-shift-current Hall plate pair is matched with "Differentail to single ended Conversion amplifier." In the experiment, the offset voltage is reduced about 1/100 time than the original offset voltage.

• Journal of Electrical Engineering and information Science
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• 제2권3호
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• pp.132-138
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• 1997

Electrical characteristics of split-gate flash EEPROM with triple polysilicon is investigated in terms of effects of floating gate and offset gate. In order to search for t the effects of offset gate on programming characteristics, threshold voltage and drain current are studied with variation of control gate voltage. The programming process is believed to depend on vertical and horizontal electric field as well as offset gate length. The erase and program threshold voltage are found to be almost constant with variation of control gate voltage above 12V, while endurance test indicates degradation of program threshold voltage. With increase of offset gate length, program threshold voltage becomes smaller and the drain source voltage just after program under constant control gate voltage becomes higher.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.971-974
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• 1999

A offset compensated class A bipolar second-generation current conveyor (CCII) for high-accuracy current-mode signal processing was proposed. The CCII adopts two diode-connection transistor between voltage input and voltage output to reduce offset voltage. Experiments show that the proposed CCII has offset voltage of 0.05 ㎷, input impedance of 2 Ω and the 3-㏈ cutoff frequency of 30 MHz when used a voltage amplifier. The power dissipation is 6 ㎷.

• 전기학회논문지
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• 제58권2호
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• pp.285-291
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• 2009

In this paper, comparative analysis of offset voltage PWM method and $V_{max}-V_{mid}$ PWM method for three-phase matrix converter is addressed by using a simple analytical and graphical method. Offset voltage PWM method calculates PWM patterns in terms of offset voltage and variable slope of carrier, and it simplifies matrix converter modulation algorithm significantly. $V_{max}-V_{mid}$ PWM method generates patterns by using two phases and maintaining a remaining phase to base phase, and it is implemented in the industrial products. The most important performance criterion of modulation method is a magnitude of current ripples and it is analytically modelled. The graphical illustration of theses complex multivariable functions make per-carrier cycle and per fundamental cycle behavior of two PWM methods understood. Two modulation methods are analysed with the analytical formulas and graphics, and the analysis shows offset voltage PWM method is superior to $V_{max}-V_{mid}$ PWM method with respect to input current ripples and output voltage ripples.

• Journal of Power Electronics
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• 제13권2호
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• pp.243-249
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• 2013

This paper presents a neutral-point voltage balancing method for three-level inverter systems using a time-offset estimation scheme. The neutral-point voltage is balanced by adding a time-offset to the turn-on time of the switches. If an inaccurate time-offset is added, the neutral-point deviation still remains. An accurate time-offset is obtained through the proposed time-offset estimation scheme. This method is implemented without additional hardware, complex calculations, or analysis. The effectiveness of the proposed method is verified by experiments.

• 전기전자학회논문지
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• 제23권4호
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• pp.1140-1149
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• 2019

전압형 컨버터의 다양한 전압 합성 방법을 구현하기 위해서, 옵셋 전압을 주입하는 방법이 널리 사용되고 있다. 즉, 전압 변조 방식(pulse width modulation; PWM)들은 교류 측 전압 지령에 적절한 옵셋 전압을 주입하는 것과 수학적으로 동일하다. 이러한 옵셋 전압을 이용한 AC 단 출력 전압 합성 방법에 따라 DC 단 전압의 전압 이용률이 달라지며, 이는 모듈형 다단 컨버터(modular multilevel converter; MMC) 시스템에서도 동일하다. 따라서, DC 단의 용량이 정해져 있는 고압 직류(high voltage DC; HVDC) 송전 시스템의 경우에도 AC 단에 옵셋 전압을 이용함에 따라 AC 단으로 공급 가능한 최대 무효 전력의 크기를 변화시킬 수 있다. 본 논문에서는 대표적인 전압 변조 방식을 적용한 옵셋 전압 주입 시 합성된 AC 측 출력 전압에 따라 MMC 시스템의 레그 에너지 맥동을 수학적으로 분석하였다. 또한, 이를 실제 스케일의 400MVA급 MMC 시스템 시뮬레이션을 통해 수학적 분석의 경향성을 검증하였다.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2012년도 추계학술대회
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• pp.848-851
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• 2012

본 논문에서는 듀얼 커패시터를 이용하여 Opamp에서 발생하는 옵셋 전압을 효과적으로 저감 시키는 회로를 소개한다. 제안하는 회로는 기존 Auto-zeroing 방식의 옵셋 전압 저감회로에서 가지는 단점을 보완하기 위해 커패시터와 mos스위치를 추가하였고, Chopping 방식을 응용하여 고주파수에서 효과적으로 옵셋 전압이 저감되도록 설계하였다. 실험은 TSMC 1.8V, $0.18{\mu}m$ 공정을 이용하여 시뮬레이션 및 레이아웃 설계를 하였고, 실험 조건하에 1Ghz의 주파수에서 5mV 이하의 옵셋 전압이 발생되었다. 이를 통해 기존의 Auto-zeroing 옵셋 저감 방식과 비교하여 옵셋 전압이 효과적으로 저감된 것을 확인하였다.