• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.5
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• pp.391-396
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• 2022

In this study, a new voltage-balancing dual-active bridge converter that integrates a DAB converter with a voltage balancer is proposed for a bipolar DC distribution system. The proposed converter is configured to connect two loads to the transformer secondary center tap of the DAB converter, and no additional components are added. The proposed converter has the same operation as the conventional DAB converter, and it makes both output voltages similar. Moreover, the imbalanced current offset between the two loads is bypassed only on the secondary side of the transformer. Consequently, the proposed converter integrates a voltage balancer without any additional components, and no additional loss occurs in the corresponding components. Thus, high efficiency and high power density can be achieved. The feasibility of the proposed converter is verified using 3 kW prototypes under 380 V input and 190/190 V output conditions.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.259-259
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• 2016

반도체 산업 전반에 걸쳐 이루어지고 있는 연구는 소자를 더 작게 만들면서도 구동능력은 우수한 소자를 만들어내는 것이라고 할 수 있다. 따라서 소자의 미세화와 함께 트랜지스터의 구동능력의 향상을 위한 기술개발에 대한 필요성이 점차 커지고 있으며, 고유전(high-k)재료를 트랜지스터의 게이트 절연막으로 이용하는 방법이 개발되고 있다. High-k 재료를 트랜지스터의 게이트 절연막에 적용하면 낮은 전압으로 소자를 구동할 수 있어서 소비전력이 감소하고 소자의 미세화 측면에서도 매우 유리하다. 그러나, 초미세화된 소자를 제작하기 위하여 high-k 절연막의 두께를 줄이게 되면, 전기적 용량(capacitance)은 커지지만 에너지 밴드 오프셋(band-offset)이 기존의 실리콘 산화막(SiO2)보다 작고 또한 열공정에 의해 쉽게 결정화가 이루어지기 때문에 누설전류가 발생하여 소자의 열화를 초래할 수 있다. 따라서, 최근에는 이러한 문제를 해결하기 위하여 게이트 절연막 엔지니어링을 통해서 누설전류를 줄이면서 전기적 용량을 확보할 수 있는 연구가 주목받고 있다. 본 실험에서는 high-k 물질인 Ta2O5와 SiO2를 적층시켜서 누설전류를 줄이면서 동시에 높은 캐패시턴스를 달성할 수 있는 게이트 절연막 엔지니어링에 대한 연구를 진행하였다. 먼저 n-type Si 기판을 표준 RCA 세정한 다음, RF sputter를 사용하여 두께가 Ta2O5/SiO2 = 50/0, 50/5, 50/10, 25/10, 25/5 nm인 적층구조의 게이트 절연막을 형성하였다. 다음으로 Al 게이트 전극을 150 nm의 두께로 증착한 다음, 전기적 특성 개선을 위하여 furnace N2 분위기에서 $400^{\circ}C$로 30분간 후속 열처리를 진행하여 MOS capacitor 소자를 제작하였고, I-V 및 C-V 측정을 통하여 형성된 게이트 절연막의 전기적 특성을 평가하였다. 그 결과, Ta2O5/SiO2 = 50/0, 50/5, 50/10 nm인 게이트 절연막들은 누설전류는 낮지만, 큰 용량을 얻을 수 없었다. 한편, Ta2O5/SiO2 = 25/10, 25/5 nm의 조합에서는 충분한 용량을 확보할 수 있었다. 적층된 게이트 절연막의 유전상수는 25/5 nm, 25/10 nm 각각 8.3, 7.6으로 비슷하였지만, 문턱치 전압(VTH)은 각각 -0.64 V, -0.18 V로 25/10 nm가 0 V에 보다 근접한 값을 나타내었다. 한편, 누설전류는 25/10 nm가 25/5 nm보다 약 20 nA (@5 V) 낮은 것을 확인할 수 있었으며 절연파괴전압(breakdown voltage)도 증가한 것을 확인하였다. 결론적으로 Ta2O5/SiO2 적층 절연막의 두께가 25nm/10nm에서 최적의 특성을 얻을 수 있었으며, 본 실험과 같이 게이트 절연막 엔지니어링을 통하여 효과적으로 누설전류를 줄이고 게이트 용량을 증가시킴으로써 고집적화된 소자의 제작에 유용한 기술로 기대된다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.69-76
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• 2008

This work proposes a 12b 1kS/s 65uA 0.35um CMOS algorithmic ADC for sensor interface applications such as accelerometers and gyro sensors requiring high resolution, ultra-low power, and small size simultaneously. The proposed ADC is based on an algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. Two versions of ADCs are fabricated with a conventional open-loop sampling scheme and a closed-loop sampling scheme to investigate the effects of offset and 1/f noise during dynamic operation. Switched bias power-reduction techniques and bias circuit sharing reduce the power consumption of amplifiers in the SHA and MDAC. The current and voltage references are implemented on chip with optional of-chip voltage references for low-power SoC applications. The prototype ADC in a 0.35um 2P4M CMOS technology demonstrates a measured DNL and INL within 0.78LSB and 2.24LSB, and shows a maximum SNDR and SFDR of 60dB and 70dB in versionl, and 63dB and 75dB in version2 at 1kS/s. The versionl and version2 ADCs with an active die area of $0.78mm^2$ and $0.81mm^2$ consume 0.163mW and 0.176mW at 1kS/s and 2.5V, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2395-2402
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• 2013

An active-RC channel selection filter (CSF) with the bandwidth of 40MHz and the improved linearity is proposed in this paper. The proposed CSF is the fifth butterworth filter which consists of a first order low pass filter, two second order low pass filters of a biquad architecture, and DC feedback circuit for cancellation of DC offset. To improve the linearity of the CSF, a body node of a MOSFET for a switch is connected to its source node. The bandwidth of the designed CSF is selected to be 10MHz, 20MHz and 40MHz and its voltage gain is controlled by 6 dB from 0 dB to 24 dB. The proposed CSF is designed by using 40nm 1-poly 8-metal CMOS process with a 1.2V. When the designed CSF operates at the bandwidth of 40 MHz and voltage gain of 0 dB, the simulation results of OIP3, in-band ripple, and IRN are 31.33dBm, 1.046dB, and 39.81nV/sqrt(Hz), respectively. The power consumption and layout area are $450{\times}210{\mu}m^2$ and 6.71mW.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.12
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• pp.1167-1172
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• 2013

This paper presents a X-band doppler radar with high conversion gain using a self-oscillating-mixer(SOM) that oscillation and frequency mixing is realized at the same time. To improve phase noise of the SOM oscillator, a ${\lambda}/2$ slotted square patch resonator(SSPR) was proposed, which shows high Q-factor of 175.4 and the 50 % reduced circuit area compared to the conventional resonator. To implement the low power system, low biasing voltage of 1.7 V was supplied. To enhance the conversion gain of the SOM, bias circuit is configured near the pinch-off region of transistor, and the conversion gain was optimized. The output power of the proposed SOM was -3.16 dBm at 10.65 GHz. A high conversion gain of 9.48 dB was obtained whereas DC Power consumption is relatively low about 7.65 mW. The phase noise is -90.91 dBc/Hz at 100 kHz offset. The figure-of-merit(FOM) of the proposed SOM was measured as -181.8 dBc/Hz, which is supplier to other SOMs by more than about 7 dB.

• Journal of IKEEE
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• v.14 no.1
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• pp.65-74
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• 2010

The Digital TV(DTV) standard has ushered in a new era in TV broadcasting and raised a great demand for DTV tuners. There are many challenges in designing a DTV tuner, of which the most difficult part is the frequency synthesizer. This paper presents the design of a frequency synthesizer for DTV Tuners in a $0.18{\mu}m$ CMOS process. It satisfies the DTV(ATSC) frequency band(54~806MHz). A scheme is proposed to cover the full band using only one VCO. The VCO has been designed to operate at 1.6~3.6GHz band such that the LO pulling effect is minimized, and reliable broadband characteristics have been achieved by reducing the variations of VCO gain and frequency step. The simulation results show that the designed VCO has gains of 59~94MHz(${\pm}$17.7MHz/V,${\pm}$23%) and frequency steps of 26~42.5MHz(${\pm}$8.25MHz/V,${\pm}$24%), and a very wide tuning range of 76.9%. The designed frequency synthesizer has a phase noise of -106dBc/Hz at 100kHz offset, and the lock time is less than $10{\mu}$sec. It consumes 20~23mA from a 1.8V supply, and the chip size including PADs is 2.0mm${\times}$1.8mm.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.4
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• pp.143-148
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• 2020

In the case of a system that detects and controls the phase of an alternating voltage, the analog control method compensates the phase offset part by filtering for the detected phase and applies it to the control. However, in the digital control method, precise control cannot be achieved due to an error between the operating frequency of the microprocessor or the microcontroller and the input phase time when controlled using such phase detection. In general, when the method used is a certain time, the accumulated error is compensated and adjusted at random. To solve this problem, a method of detecting a zero point in real time and compensating for the operating frequency of the microprocessor is needed. Therefore, the research to be performed in this paper to reduce these errors and apply them to precise digital control is as follows. 1) Research on how to implement Zero Crossing Detection algorithm through simulation modeling to compensate the zero point to match the operating frequency through detection. 2) A study on the method of detecting zero points in real time through the Zero Crossing Detection design using a microcontroller and compensating for the operating frequency of the microprocessor. 3) A study on the estimation of the rotor position of BLDC motors using the Zero Crossing Detection circuit.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.4
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• pp.381-388
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• 2015

In this paper, a wireless video streaming system is designed and implemented for TV white space applications. It consists of a RF transceiver module, a digital modem, a camera, and a LCD screen. A VGA resolution video is captured by a camera, modulated by modem, and transmitted by RF transceiver module, and finally displayed at a destination 2.6-inch LCD screen. The RF transceiver is based on direct-conversion architecture. Image leakage is improved by low pass filtering LO, which successfully covers the TVWS. Also, DC offset problem is solved by current steering techniques which control common mode level at DAC output node. The output power of the transmitter and the minimum sensitivity of the receiver is +10 dBm and -82 dBm, respectively. The channel bandwidth is tunable among 6, 7 and 8 MHz according to regulations and standards. Digital modem is realized in Kintex-7 FPGA. Data rate is 9 Mbps based on QPSK and 512ch OFDM. A VGA video is successfully streamed through the air by using the developed TV white-space RF communication module.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.71-80
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• 2007

This paper presents a new push-push VCO technique that extracts a second harmonic output signal from a capacitive commonnode in a negativegm oscillator topology. The generation of the $2^{nd}$ harmonics is accounted for by the nonlinear current-voltage characteristic of the emitter-base junction diode causing; 1) significant voltage clipping and 2) different rising and falling time during the switching operation of core transistors. Comparative investigations show the technique is more power efficient in the high-frequency region that a conventional push-push technique using an emitter common node. Prototype 12GHz and 17GHz MMIC VCO were realized in GaInP/GaAs HBT technology. They have shown nominal output power of -4.3dBm and -5dBm, phase noise of -108 dBc/Hz and -110.4 dBc/Hz at 1MHz offset, respectively. The phase noise results are also equivalent to a VCO figure-of-merit of -175.8 dBc/Hz and -184.3 dBc/Hz, while dissipate 25.68mW(10.7mA/2.4V) and 13.14mW(4.38mA/3.0V), respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.5
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• pp.1125-1134
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• 2011

In this paper a wideband frequency synthesizer is designed for DTV tuners using a $0.18{\mu}m$ CMOS process. It satisfies the DTV frequency band(48~1675MHz). A scheme is proposed to cover the full band using only one VCO and reliable broadband characteristics are achieved by reducing the variations of VCO gains and frequency steps. The simulation results show that the designed VCO has frequency range of 1.85~4.22GHz, phase noise at 4.22GHz of -89.7dBc/Hz@100kHz, gains of 62.4~95.8MHz/V(${\pm}21.0%$) and frequency steps of 22.9~47.9MHz(${\pm}35.3%$). The designed VCO has a phase noise of -89.75dBc/Hz at 100kHz offset. The designed synthesizer has a lock time less than $0.15{\mu}s$. The measured VCO tuning range is 2.05~3.4GHz. The frequency range is shifted down but still satisfy the target range owing to the design for enough margin. The designed circuit consumes 23~27mA from a 1.8V supply, and the chip size including PADs is $2.0mm{\times}1.5mm$.