• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.530-534
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• 2002

In the thesis, For improving the Stability of VCHRO(Voltage Controlled Hair-pin Resonator Oscillator) the new structure using the parallel feedback of the second harmonic is proposed for self-phase locking effect. This module is composed of wilkinson divider, frequency doubler, directional coupler, and bandpass filter using a hair-pin resonator, which are integrated into miniaturized hybrid circuit. The module exhibits output power of 2.5 dBm at 19.5 GHz, -29.83 dBc fundamental frequency suppression and -76.52 dBc/Hz phase noise at 10 kHz offset frequency from carrier of center frequency 19.5 GHz.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.9
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• pp.30-37
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• 2000

In this paper, design and fabrication of miniature voltage-controlled oscillator(VCO) is discussed . Based on the two-port circuit analysis technique, VCO for 900MHz cellular mobile phone is designed and circuit parameters are optimized using the circuit simulator. Using the optimized design parameters, miniature VCO with 6${\times}$6${\times}$1.8 mm$^3$(0.065cc) dimensions is fabricated and experimented. Experimental results show that implemented VCO has -3.5 dBm output power level and 45MHz tunung range, respectively, and has -101.5dB/Hz Phase noise performance at 10 KHz frequency offset.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12B
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• pp.1695-1702
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• 2001

This paper describes a design of CMOS infrared (IR) wireless data link IC which can be used in IrDA(Infrared Data Association) application from 4 Mb/s to 100 Mb/s The implemented chip consists of variable gain transimpedance amplifier which has a gain range from 60 dB to 100 dB, AGC (automatic gain control) circuits, AOC(automatic offset control) loop, 4 PPM (pulse position modulation) modulator/demodulator and DLL(delay locked loops). This infrared optical link If was implemented using commercial 0.25 um 1-poly 5-metal CMOS process. The chip consumes 25 mW at 100 Mb/s with 2.5 V supply voltage excluding buffer amplifier. The die area of prototype IC is 1.5 mm $\times$ 1 mm.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.12
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• pp.32-37
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• 2000

We proposed to a new method of the aperture coupled microstrip antenna with T-shaped feeding slot. We analyzed method of enhancing the bandwidth of the antenna using FDTD. And the antenna parameters are optimized to get maximum bandwidth. We also calculated the progress process of waves and the distribution of electric field in the time domain. We also calculated return loss, VSWR, input impedance, radiation pattern in the frequency domain by Fourier transforming the time domain results, respectively. It was found that the bandwidth of this antenna changes length and width of the patch, length and width of the slot, length of T-shaped feedline, position of the offset. Measured % bandwidth was 49.2 % in the center frequency 2.5 GHz. These results were in relatively food accordance with calculated values.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.3
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• pp.231-239
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• 1999

An improved version of current-regulated delta modulator (CRDM) is investigated for the output cunent control of v voltage-source inverters that have transformer-coupled series resonant load and are operated at the resonant frequency. Conventional CRDM has not only CUlTent offset problem but also transformer flux saturation problem when i it is applied to induction heating systems that have transformel-coupled loads. To cope with these problems, the effect of flux saturation is analysed, and simple method to av이d the problem is proposed. And integral type of CRDM is a adopted to remove the cunent offset. The boundaries of integrator gain for stable operation is calculated using the c concept of sliding mode controL The validity of proposed strategy is vel퍼ed through simulations and prototype e experiments.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.19-27
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• 2007

This paper presents power supply-insensitive Gbps low power LVDS I/O circuits. The proposed LVDS I/O has been designed and simulated using 1.8V, $0.18\;{\mu}m$ TSMC CMOS Process. The LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and an output stage with the switched capacitor common mode feedback(SC-CMFB). The differential phase splitter generates a pair of differential signals which provides a balanced duty $cycle(50{\pm}2%)$ and phase difference$(180{\pm}0.2^{\circ})$ over a wide supply voltage range. Also, $V_{OD}$ voltage is 250 mV which is the smallest value of the permissible $V_{OD}$ range for low power operation. The output buffer maintains the required $V_{CM}$ within the permissible range$(1.2{\pm}0.1V)$ due to the SC-CMFB. The receiver covers a wide input DC offset $range(0.2{\sim}2.6\;V)$ with 38 mV hysteresis and Produces a rail-to-rail output over a wide supply voltage range. Beside, the designed receiver has 38.9 dB gain at 1 GHz, which is higher than conventional receivers.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.4
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• pp.527-536
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• 2014

In this paper, the 50kW aerogenerator which is applicable to the microgrid was designed and analyzed by using commercial simulation program Maxwell 2D. Particularly, the suggested PMSG to reduce the cogging torque introduced the offset and skew concept. The suggested optimal value of offset and skew was decided by 2mm and 60 degree of electric angle. The simulation results of the PMSG when load operation condition showed the average harmonic distortion 1.3%, voltage 322.41V, current 94.95A, and iron loss 9.73W, eddy current loss 73.68W, copper loss 3.52kW. The capacity of aerogenerator calculated 61.56kW, and the suggested design process can be applied to higher capacity generator.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.10
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• pp.1151-1156
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• 2012

In this paper, the baseband filter is proposed in order to maintain a constant sensitivity regardless of distances for 77 GHz automotive radar system. Using existing DCOC loop circuit can remove DC offset and also cancel differences of received power depending on the distance. Measured results show that the maximum gain is 51 dB and high pass cutoff frequency can be tuned from 5 kHz to 15 kHz. The slope of high pass filter can be tuned from -10 to -40 dB/decade for the distance compensation. The measured NF and IIP3 are 26 dB and +4.5 dBm with 4.3 mA at 1.0 V supply voltage, respectively. The fabricated die size $500{\mu}m{\times}1,050{\mu}m$ excluding the in/out pads.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.906-911
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• 2004

In this paper, a VCDRO(Voltage Control Dielectric Resonator Oscillator) applied to FMCW(Frequency Modulated Continuous Wave)Radar as stable source is implemented and constructed with a MESFET(Metal-semiconductor Field-Effect Transistor) for low noise, a dielectric resonate. of high frequency selectivity, and high Q varator diode to obtain a good phase noise performance and stable sweep characteristics. The designed circuits is simulated thrash harmonic balance simulation technique to provide the optimum performance. The measured result of a fabricated VCDRO shows that output is 2.22㏈m at 12.05GHz, harmonic suppression -30㏈c, phase noise -130㏈c at 100KHz offset, and sweep range of varator diode $\pm$18.7MHz, respectively. This oscillator will be available to FMCW Radar.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.152-159
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• 2016

This paper describes an offset and 1/f noise cancellation technique based hall sensor signal processor. The hall sensor outputs a hall voltage from the input magnetic field, which direction is orthogonal to hall plate. The two major elements to complete the hall sensor operation are: the one is a hall sensor to generate hall voltage from input magentic field, and the other one is a hall signal process system to cancel the offset and 1/f noise of hall signal. The proposed hall sensor splits the hall signal and unwanted signals(i.e. offset and 1/f noise) using a spinning current biasing technique and chopper stabilizer. The hall signal converted to 100 kHz and unwanted signals stay around DC frequency pass through chopper stabilizer. The unwanted signals are bloked by highpass filter which, 60 kHz cut off freqyency. Therefore only pure hall signal is enter the ADC(analog to dogital converter) for digitalize. The hall signal and unwanted signal at the output of an amplifer and highpass filter, which increase the power level of hall signal and cancel the unwanted signals are -53.9 dBm @ 100 kHz and -101.3 dBm @ 10 kHz. The ADC output of hall sensor signal process system has -5.0 dBm hall signal at 100 kHz frequency and -55.0 dBm unwanted signals at 10 kHz frequency.