• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.16 no.1
• /
• pp.233-238
• /
• 2016

Recently, the multi-core processor architecture is widely adopted in the embedded processors for enhancing its performance. Multi-core processors are classified either as symmetric or asymmetric. Asymmetric multicore processors are known to score higher performance and more efficient than symmetric multi-core processors. In order to study the performance enhancement of asymmetric multi-core embedded processors over the symmetric ones, the trace-driven simulation has been executed for various asymmetric embedded dual-core, quad-core, octa-core and hexadeca-core processors and compared with the symmetric ones of similar hardware budget using MiBench benchmarks as input.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.15 no.5
• /
• pp.219-224
• /
• 2015

Recently, the multi-core processor architecture is widely used in the digital signal processors for enhancing its performance. Multi-core processors are classified either as symmetric or asymmetric. Asymmetric multi-core processors are known to have higher performance and more efficient than symmetric multi-core processors. In order to study the performance enhancement of asymmetric multi-core digital signal processors over the symmetric ones, the trace-driven simulation has been executed for various asymmetric quad-core, octa-core and hexadeca-core digital signal processors and compared with the symmetric ones of similar hardware budget using UTDSP benchmarks as input.

• Macromolecular Research
• /
• v.15 no.4
• /
• pp.324-329
• /
• 2007

An octa-functional alkoxyamine initiator, with the 2,2,6,6-tetramethyl-l-piperidinyloxy (TEMPO) free radical, was synthesized based on resorcinarene, with its efficiency to initiate the nitroxide-mediated free radical copolymerization of styrene and methyl methacrylate (MMA) described. A difunctional analogue of this initiator was also synthesized, using resorcinol as the core molecule. The structures of the resulting initiators were confirmed by homolysis studies based on electron spin resonance spectroscopy and molecular modeling. The polymerization behavior and characteristics of the polymers obtained using these two initiators were also compared. Well-defined star-shaped and linear random copolymers, with low polydispersities and controlled molecular weights, were prepared. The efficiencies of these initiators towards copolymerization, as well as the parameters permitting the formation of well-defined polymers, were also investigated. The reactivity ratios were $r_a=0.42(a=styrene)\;and\;r_b=0.33(b=MMA)$ for the octa-functional initiator system and $r_a=0.45\;and\;r_b=0.39$ for the difunctional initiator system.

• Mycobiology
• /
• v.30 no.3
• /
• pp.117-127
• /
• 2002

Cleistothecial development in Aspergillus nidulans(teleomorph, Emericella nidulans) was examined with the transmission electron microscopy. Cleistothecial initial was a small coiled lump of cells, ca. 6 ${\mu}m$ in diameter, which was consisted of a slightly swollen core with a short "tail" hypha. Initials were wrapped with a loose layer of hyphae. Core cells of cleistothecial initials were broad and multinucleated at first, then formed dikaryotic ascogenous cells, followed by post-meiotic tetra-nucleate or octa-nucleate protoasci and finally mature ascospores. Croziers were formed early during cleistothecium development. The peridial layer of mature cleistothecia was derived from the wrapping hyphae which originally invested the young cleistothecium. Completion of peridial layers development was associated with the depositing of a non-enzyme reactive material around peridial cells. $H\ddot{u}lle$ cell formation during the cleistothecial development appeared to be somewhat coordinated with the developmental stages of cleistothecium.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.14 no.3
• /
• pp.163-169
• /
• 2014

Recently, the importance of multicore processor system is growing rapidly. Multicore processors are classified either as symmetric or asymmetric. Asymmetric multicore processors consist of a high performance complex core and number of low performance simple cores, and are known to be more efficient than symmetric multicore processors. Therefore, performance impact on various configurations of asymmetric multi-core processor needs to be studied. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed for different asymmetric quad-core and octa-core processors and compared to the corresponding symmetric ones.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.9
• /
• pp.1778-1784
• /
• 2016

we improved the performance by parallelizing lane detection algorithms. Lane detection, as a intellectual assisting system, helps drivers make an alarm sound or revise the handle in response of lane departure. Four kinds of algorithms are implemented in order as following, Gaussian filtering algorithm so as to remove the interferences, gray conversion algorithm to simplify images, sobel edge detection algorithm to find out the regions of lanes, and hough transform algorithm to detect straight lines. Among parallelized methods, the data level parallelism algorithm is easy to design, yet still problem with the bottleneck. The high-speed data level parallelism is suggested to reduce this bottleneck, which resulted in noticeable performance improvement. In the result of applying actual road video of black-box on our parallel algorithm, the measurement, in the case of single-core, is approximately 30 Frames/sec. Furthermore, in the case of octa-core parallelism, the data level performance is approximately 100 Frames/sec and the highest performance comes close to 150 Frames/sec.

• Journal of Digital Convergence
• /
• v.13 no.12
• /
• pp.381-390
• /
• 2015

One of the fundamental requirements of entertainment applications is interactivity with users. The mobile device such as the smartphone, however, does not guarantee it due to the limit of the application processor's computing power, memory size and available electric power of the battery. This paper proposes a methodology to boost responsiveness of interactive applications by taking advantage of the parallel architecture of mobile devices which, for instance, have dual-core, quad-core or octa-core. To harness the multi-core architecture, it exploits the POSIX thread, a platform-independent thread library to be able to be used in various mobile platforms such as Android, iOS, etc. As a useful application example of the methodology, a heavy matrix calculation function was transformed to a parallelized version which showed around 2.5 ~ 3 times faster than the original version in a real-world usage environment.

• Applied Microscopy
• /
• v.46 no.1
• /
• pp.6-13
• /
• 2016

Fluorescence lifetime imaging microscopy (FLIM) has been considered an effective technique to investigate chemical properties of the specimens, especially of biological samples. Despite of this advantageous trait, researchers in this field have had difficulties applying FLIM to their systems because acquiring an image using FLIM consumes too much time. Although analog mean-delay (AMD) method was introduced to enhance the imaging speed of commonly used FLIM based on time-correlated single photon counting (TCSPC), a real-time image reconstruction using AMD method has not been implemented due to its data processing obstacles. In this paper, we introduce a real-time image restoration of AMD-FLIM through fast parallel data processing by using Threading Building Blocks (TBB; Intel) and octa-core processor (i7-5960x; Intel). Frame rate of 3.8 frames per second was achieved in $1,024{\times}1,024$ resolution with over 4 million lifetime determinations per second and measurement error within 10%. This image acquisition speed is 184 times faster than that of single-channel TCSPC and 9.2 times faster than that of 8-channel TCSPC (state-of-art photon counting rate of 80 million counts per second) with the same lifetime accuracy of 10% and the same pixel resolution.

• Journal of the Korea Computer Graphics Society
• /
• v.26 no.1
• /
• pp.17-25
• /
• 2020

We present a novel multi-core CPU based parallel algorithm for the cell-connectivity information extraction algorithm, which is one of the preprocessing steps for volume rendering of unstructured grid data. We first check the synchronization issues when parallelizing the prior serial algorithm naively. Then, we propose a 3-step parallel algorithm that achieves high parallelization efficiency by removing synchronization in each step. Also, our 3-step algorithm improves the cache utilization efficiency by increasing the spatial locality for the duplicated triangle test process, which is the core operation of building cell-connectivity information. We further improve the efficiency of our parallel algorithm by employing a memory pool for each thread. To check the benefit of our approach, we implemented our method on a system consisting of two octa-core CPUs and measured the performance. As a result, our method shows continuous performance improvement as we add threads. Also, it achieves up to 82.9 times higher performance compared with the prior serial algorithm when we use thirty-two threads (sixteen physical cores). These results demonstrate the high parallelization efficiency and high cache utilization efficiency of our method. Also, it validates the suitability of our algorithm for large-scale unstructured data.