• International Journal of Aeronautical and Space Sciences
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• 제4권1호
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• pp.88-98
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• 2003

Compared to the noise limits (CAN7) specified in ICAO Annex 16 for civil helicopters, the Lynx helicopter equipped with BERP blades has only 0.2 EPNdB margin in the approach case although it has more than 4 EPNdB margin in fly-over and take-off conditions. The objectives of the study described in this paper were to devise a low noise main rotor blade for the Lynx using UEAF combined with the high resolution airload model ACROT. A design requirement is that the new blade, KBERP (Korean BERP) blade should achieve a significant reduction in noise during approach(at least 6EPNdB margin) without any noise penalty in fly-over and take-off conditions and minimal performance penalty. It was decided to investigate a tip modification to the BERP blade, employing the twin vortex concept to reduce the BVI noise and to retain the excellent high speed performance characteristics of BERP. Through the parametric study, the KBERP blade with optimized twin vortices has at least a 9 EPNdB noise margin in approach flight condition with only a small penalty in fly-over and take-off conditions. The KBERP tip is thus a very cost effective wav to reduce BVI noise during approach.

• 대한수학회지
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• 제59권2호
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• pp.217-233
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• 2022

Although machine learning shows state-of-the-art performance in a variety of fields, it is short a theoretical understanding of how machine learning works. Recently, theoretical approaches are actively being studied, and there are results for one of them, margin and its distribution. In this paper, especially we focused on the role of margin in the perturbations of inputs and parameters. We show a generalization bound for two cases, a linear model for binary classification and neural networks for multi-classification, when the inputs have normal distributed random noises. The additional generalization term caused by random noises is related to margin and exponentially inversely proportional to the noise level for binary classification. And in neural networks, the additional generalization term depends on (input dimension) × (norms of input and weights). For these results, we used the PAC-Bayesian framework. This paper is considering random noises and margin together, and it will be helpful to a better understanding of model sensitivity and the construction of robust generalization.

• 응용통계연구
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• 제16권2호
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• pp.261-271
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• 2003

서포트 벡터 기계(Support Vector Machines, SVMs)에서의 일반화 오차의 경계는 훈련점들과 분리 초평면 사이의 최소의 거리에 의존한다. 특히, 소프트 마진 알고리즘은 목표 마진과 slack 벡터의 놈들에 의하여 경계가 결정된다. 이 논문에서는, 자료들에 있어서 잡음들에 의한 오염들을 직접적으로 고려하는 새로운 소프트 마진 알고리즘을 공식화하였다. 그리고, 수치적 예제를 통하여, 제안된 방법과 기존의 소프트 마진 알고리즘을 비교하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권3호
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• pp.370-377
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• 2017

This paper presents a simple noise margin (NM) model of MOS current mode logic (MCML) gates especially in CMOS processes where a large device mismatch deteriorates logic reliability. Trade-offs between speed and logic reliability are discussed, and a simple yet accurate NM equation to capture process-dependent degradation is proposed. The proposed NM equation is verified for 130-nm, 110-nm, 65-nm, and 40-nm CMOS processes and has errors less than 4% for all cases.

• ETRI Journal
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• 제41권3호
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• pp.383-395
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• 2019

Clock Controlled Dual keeper Domino logic structures (CCDD_1 and CCDD_2) for achieving a high-speed performance with low power consumption and a good noise margin are proposed in this paper. The keeper control circuit comprises an additional PMOS keeper transistor controlled by the clock and foot node voltage. This control mechanism offers abrupt conditional control of the keeper circuit and reduces the contention current, leading to high-speed performance. The keeper transistor arrangement also reduces the loop gain associated with the feedback circuitry. Hence, the circuits offer less delay variability. The design and simulation of various wide fan-in designs using 180 nm CMOS technology validates the proposed CCDD_1 and CCDD_2 designs, offering an increased speed performance of 7.2% and 8.5%, respectively, over a conventional domino logic structure. The noise gain margin analysis proves good robustness of the CCDD structures when compared with a conventional domino logic circuit configuration. A Monte Carlo simulation for 2,000 runs under statistical process variations demonstrates that the proposed CCDD circuits offer a significantly reduced delay variability factor.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권2호
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• pp.118-129
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• 2010

A lower-threshold-voltage (LVth) SRAM cell with an elevated cell biasing scheme, which enables to reduce the random threshold-voltage (Vth) variation and to alleviate the stability-degradation caused by word-line (WL) and cell power line (VDDM) disturbed accesses in row and column directions, has been proposed. The random Vth variation (${\sigma}Vth$) is suppressed by the proposed LVth cell. As a result, the LVth cell reduces the variation of static noise margin (SNM) for the data retention, which enables to maintain a higher SNM over a larger memory size, compared with a conventionally being used higher Vth (HVth) cell. An elevated cell biasing scheme cancels the substantial trade-off relationship between SNM and the write margin (WRTM) in an SRAM cell. Obtained simulation results with a 45-nm CMOS technology model demonstrate that the proposed techniques allow sufficient stability margins to be maintained up to $6{\sigma}$ level with a 0.5-V data retention voltage and a 0.7-V logic bias voltage.

• 전기학회논문지
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• 제58권6호
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• pp.1157-1165
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• 2009

In AC-PDP, it is necessary to achieve high luminance efficiency, high luminance and high definition by adopting technologies such as high xenon concentration, MgO doping, and long gap. However, it is very difficult to apply above technologies because they make the driving voltage margin reduced. Especially, high Xe concentration technology for high efficacy makes not only the driving voltage margin reduced but also the stability of reset discharge decreased at low temperature. In this paper, we studied temperature and voltage dependent stability of reset discharge and present the experimental results of the discharge characteristics at low temperature. In addition, we suggested the mechanism of bright noise and black noise at low temperature. Finally, we proposed double reset waveform to improve the bright noise and descending scan time method to improve the black noise.

• ETRI Journal
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• 제26권6호
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• pp.583-588
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• 2004

In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of $3.63{\mu}m^2$. We designed a 1Mb DRAM with an open bit-line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when $V_{cc}$ is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.

• 한국항공우주학회지
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• 제32권8호
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• pp.138-144
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• 2004

우주환경에서 운용되는 위성은 상호 유기적으로 연결된 다양한 전자장비에서 방출하는 전도성/복사성 에너지 결함에 의해 다양한 노이즈를 발생하게 되는데, 이러한 노이즈는 위성 시스템과 탑재체의 전자기적인 영향에 의하여 주요 기능에 중대한 결함을 유발시킬 수 있다 이에 위생 시스템은 개발 단계에서부터 전자파환경에 대한 영향을 최소화하기 위한 시스템 설계 검증이 요구된다. 위성 시스템에서 검증하여야 하는 전자파환경시험은 위성으로부터 방출되는 전도성/복사성 노이즈 레벨측정과 이러한 노이즈환경에서 위성의 정상운용을 검증하는 감응성 시험이 있다. 다목적실용위성 2호의 전도성 전자파환경에서의 시스템 설계 검증은 PCU가 전원을 각 유닛에 분배하는 그 과정에서 전원선에서 방출하는 전도성 방출특성을 측정하여 시스템에서 통제하는 전자파 규격에 적합한지를 검증하고, 이러한 방출 레벨로부터 6dB 시스템 안전성마진을 고려한 레벨의 전도성 노이즈를 전원선에 인가하여 시스템의 성능을 검증하는 것이다. 본 논문에서는 다목적실용위성 2호의 전도성 특성을 검증하기 위해 ETB에서 수행한 시스템 검증결과 및 노이즈 요소 분석을 제시하였으며, 노이즈요소 분석 결과는 FM EMC 시험에 반영될 것이다.

• 한국전기전자재료학회논문지
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• 제22권3호
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• pp.239-247
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• 2009

In AC-PDP, it is necessary to achieve high luminance efficacy, high luminance and high resolution by adopting technologies such as high Xenon concentration, MgO doping, and long gap. However, it is very difficult to apply above technologies because they reduce driving voltage margin. For example, doping of MgO reduces driving voltage but introduces new problems such as increased temperature dependency of discharge, which result in larger variations in driving margin at different temperatures. In this paper, we present the experimental results of the characteristics of temperature-dependent discharges. In addition, we suggest the mechanism of bright noise, black noise, and high temperature mis-discharge, which depend on temperature-dependent characteristics of MgO.