• International Journal of Aeronautical and Space Sciences
• /
• v.4 no.1
• /
• pp.88-98
• /
• 2003

Compared to the noise limits (CAN7) specified in ICAO Annex 16 for civil helicopters, the Lynx helicopter equipped with BERP blades has only 0.2 EPNdB margin in the approach case although it has more than 4 EPNdB margin in fly-over and take-off conditions. The objectives of the study described in this paper were to devise a low noise main rotor blade for the Lynx using UEAF combined with the high resolution airload model ACROT. A design requirement is that the new blade, KBERP (Korean BERP) blade should achieve a significant reduction in noise during approach(at least 6EPNdB margin) without any noise penalty in fly-over and take-off conditions and minimal performance penalty. It was decided to investigate a tip modification to the BERP blade, employing the twin vortex concept to reduce the BVI noise and to retain the excellent high speed performance characteristics of BERP. Through the parametric study, the KBERP blade with optimized twin vortices has at least a 9 EPNdB noise margin in approach flight condition with only a small penalty in fly-over and take-off conditions. The KBERP tip is thus a very cost effective wav to reduce BVI noise during approach.

• Journal of the Korean Mathematical Society
• /
• v.59 no.2
• /
• pp.217-233
• /
• 2022

Although machine learning shows state-of-the-art performance in a variety of fields, it is short a theoretical understanding of how machine learning works. Recently, theoretical approaches are actively being studied, and there are results for one of them, margin and its distribution. In this paper, especially we focused on the role of margin in the perturbations of inputs and parameters. We show a generalization bound for two cases, a linear model for binary classification and neural networks for multi-classification, when the inputs have normal distributed random noises. The additional generalization term caused by random noises is related to margin and exponentially inversely proportional to the noise level for binary classification. And in neural networks, the additional generalization term depends on (input dimension) × (norms of input and weights). For these results, we used the PAC-Bayesian framework. This paper is considering random noises and margin together, and it will be helpful to a better understanding of model sensitivity and the construction of robust generalization.

• The Korean Journal of Applied Statistics
• /
• v.16 no.2
• /
• pp.261-271
• /
• 2003

Support Vector Machines (SVMs) provide a powerful performance of the learning system. Generally, SVMs tend to make overfitting. For the purpose of overcoming this difficulty, the definition of soft margin has been introduced. In this case, it causes another difficulty to decide the weight for slack variables reflecting soft margin classifiers. Especially, the error of soft margin algorithm can be bounded by a target margin and some norms of the slack vector. In this paper, we formulate a new soft margin algorithm considering the bound of corruption by noise in data directly. Additionally, through a numerical example, we compare the proposed method with a conventional soft margin algorithm.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.3
• /
• pp.370-377
• /
• 2017

This paper presents a simple noise margin (NM) model of MOS current mode logic (MCML) gates especially in CMOS processes where a large device mismatch deteriorates logic reliability. Trade-offs between speed and logic reliability are discussed, and a simple yet accurate NM equation to capture process-dependent degradation is proposed. The proposed NM equation is verified for 130-nm, 110-nm, 65-nm, and 40-nm CMOS processes and has errors less than 4% for all cases.

• ETRI Journal
• /
• v.41 no.3
• /
• pp.383-395
• /
• 2019

Clock Controlled Dual keeper Domino logic structures (CCDD_1 and CCDD_2) for achieving a high-speed performance with low power consumption and a good noise margin are proposed in this paper. The keeper control circuit comprises an additional PMOS keeper transistor controlled by the clock and foot node voltage. This control mechanism offers abrupt conditional control of the keeper circuit and reduces the contention current, leading to high-speed performance. The keeper transistor arrangement also reduces the loop gain associated with the feedback circuitry. Hence, the circuits offer less delay variability. The design and simulation of various wide fan-in designs using 180 nm CMOS technology validates the proposed CCDD_1 and CCDD_2 designs, offering an increased speed performance of 7.2% and 8.5%, respectively, over a conventional domino logic structure. The noise gain margin analysis proves good robustness of the CCDD structures when compared with a conventional domino logic circuit configuration. A Monte Carlo simulation for 2,000 runs under statistical process variations demonstrates that the proposed CCDD circuits offer a significantly reduced delay variability factor.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.10 no.2
• /
• pp.118-129
• /
• 2010

A lower-threshold-voltage (LVth) SRAM cell with an elevated cell biasing scheme, which enables to reduce the random threshold-voltage (Vth) variation and to alleviate the stability-degradation caused by word-line (WL) and cell power line (VDDM) disturbed accesses in row and column directions, has been proposed. The random Vth variation (${\sigma}Vth$) is suppressed by the proposed LVth cell. As a result, the LVth cell reduces the variation of static noise margin (SNM) for the data retention, which enables to maintain a higher SNM over a larger memory size, compared with a conventionally being used higher Vth (HVth) cell. An elevated cell biasing scheme cancels the substantial trade-off relationship between SNM and the write margin (WRTM) in an SRAM cell. Obtained simulation results with a 45-nm CMOS technology model demonstrate that the proposed techniques allow sufficient stability margins to be maintained up to $6{\sigma}$ level with a 0.5-V data retention voltage and a 0.7-V logic bias voltage.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.58 no.6
• /
• pp.1157-1165
• /
• 2009

In AC-PDP, it is necessary to achieve high luminance efficiency, high luminance and high definition by adopting technologies such as high xenon concentration, MgO doping, and long gap. However, it is very difficult to apply above technologies because they make the driving voltage margin reduced. Especially, high Xe concentration technology for high efficacy makes not only the driving voltage margin reduced but also the stability of reset discharge decreased at low temperature. In this paper, we studied temperature and voltage dependent stability of reset discharge and present the experimental results of the discharge characteristics at low temperature. In addition, we suggested the mechanism of bright noise and black noise at low temperature. Finally, we proposed double reset waveform to improve the bright noise and descending scan time method to improve the black noise.

• ETRI Journal
• /
• v.26 no.6
• /
• pp.583-588
• /
• 2004

In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of $3.63{\mu}m^2$. We designed a 1Mb DRAM with an open bit-line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when $V_{cc}$ is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.32 no.8
• /
• pp.138-144
• /
• 2004

Satellite generates a complex electromagnetic noise by conducted and radiated coupling effect of the various electrical instruments. This noise may cause serious problems on the satellite system. To minimize the electromagnetic coupling effects and maintain the system safety margin, system noise reduction technique should be applied from the beginning of the system design. The KOMPSAT-2 system is evaluated by measuring the conducted noise on system electrical power leads and verifying a 6dB system safety margin under the complex noise environment with current injection. This paper describes the KOMPSAT-2 system evaluation result performed on ETB(Electrical Test Bed) and the analysed noise element, the analysed result will be reflected on FM(Flight Model) EMC test.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.22 no.3
• /
• pp.239-247
• /
• 2009

In AC-PDP, it is necessary to achieve high luminance efficacy, high luminance and high resolution by adopting technologies such as high Xenon concentration, MgO doping, and long gap. However, it is very difficult to apply above technologies because they reduce driving voltage margin. For example, doping of MgO reduces driving voltage but introduces new problems such as increased temperature dependency of discharge, which result in larger variations in driving margin at different temperatures. In this paper, we present the experimental results of the characteristics of temperature-dependent discharges. In addition, we suggest the mechanism of bright noise, black noise, and high temperature mis-discharge, which depend on temperature-dependent characteristics of MgO.