• 전자공학회논문지B
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• 제31B권4호
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• pp.155-165
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• 1994

An analog neural network circuit of rhigh density integration is introduced. It's prototype chip is designed in 3 by 3 mm2 die. It uses only one MOSFET to implement a synapse. The number of synapses per neuron can be expanded by cascading several chips. The influence of nonlinearity in synapses is analyzed. A formalization of the back propagation which can be applied to this circuit is shown. Some simulation results are shown and disscussed.

• 전자공학회논문지B
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• 제30B권11호
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• pp.66-73
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• 1993

This paper presents an analog circuit implementation and experimental resuls of the Hopfield type neural network. The proposed architecture enables the reconfiguration betwewn feedback and feedforward networks and employs new circuit designs for the weight supply and storage, analog multilier, nd current-voltage converter, in order to achieve area efficiency as well as function al versatility. The layout design of the eight-neuron neural network is tested as an associative memory to verify its applicability to real world.

• Journal of information and communication convergence engineering
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• 제10권2호
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• pp.194-199
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• 2012

This paper proposes a novel scheme of a gray scale fingerprint image for a high-accuracy capacitive sensor chip. The conventional grayscale image scheme uses a digital-to-analog converter (DAC) of a large-scale layout or charge-pump circuit with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit for the charge sharing scheme is proposed, which uses a down literal circuit (DLC) with a floating-gate metal-oxide semiconductor transistor (FGMOS) based on a neuron model. The detection circuit is designed and simulated in a 3.3 V, 0.35 ${\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, the pixel layout size can be reduced and the image resolution can be improved.

• 대한의용생체공학회:의공학회지
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• 제17권1호
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• pp.79-84
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• 1996

A number of experimental evidences suggest that the rnun ventrolateral medulla(RVLM) is the final common pathway in the regulation of arterial blood pressure. A Voup of neurons in the RVLM, called the cardiovascular neurons (UN), show spontaneous activity temporally synchronized with the periodic cardiac cycle. These neurons affect the sympathetic nerve discharge(SND), thus are believed to be responsible for blood pressure control. The present experiment identified 98 UVNs in 42 cats based on the temporal relationships between each neuron's activity with both the cardiac cycle and SWD. In 20 UWL changes of spontaneous firing rate(FR) during the somatosympathetic reflex(SSR) were studied Five different firing patterns were observed during the pressor and depressor responses of SSR, implying that they form an interconnected neuronal circuit interacting with one another to generate efferent signals for blood pressure regulation. In the following companion paper, the firing patterns of CVN are analyzed to develop a minimal neuronal circuit model explaining the present experimental outcome.

• 대한의용생체공학회:의공학회지
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• 제17권1호
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• pp.71-80
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• 1996

A number of experimental evidences suggest that the rnun ventrolateral medulla(RVLM) is the final common pathway in the regulation of arterial blood pressure. A Voup of neurons in the RVLM, called the cardiovascular neurons (UN), show spontaneous activity temporally synchronized with the periodic cardiac cycle. These neurons affect the sympathetic nerve discharge(SND), thus are believed to be responsible for blood pressure control. The present experiment identified 98 UVNs in 42 cats based on the temporal relationships between each neuron's activity with both the cardiac cycle and SWD. In 20 UWL changes of spontaneous firing rate(FR) during the somatosympathetic reflex(SSR) were studied Five different firing patterns were observed during the pressor and depressor responses of SSR, implying that they form an interconnected neuronal circuit interacting with one another to generate efferent signals for blood pressure regulation. In the following companion paper, the firing patterns of CVN are analyzed to develop a minimal neuronal circuit model explaining the present experimental outcome.

• 전자공학회논문지CI
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• 제37권5호
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• pp.45-53
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• 2000

0.8㎛ 단일 폴리 CMOS 집적회로로 구현된 혼돈 뉴런의 동적 응답 특성을 분석하였다. 구현된 CMOS 혼돈 뉴런의 시그모이드 출력함수와 혼돈 발생회로 블록에 대한 일련의 수식 모델을 구하여 혼돈 뉴런의 동적 응답특성, 즉 뉴런 내부상태의 분기도 및 초기값 의존성을 보여주는 리아프노프 지수와 평균 발화율, 시간 및 주파수 응답 등 다양한 특성들을 수치해석적으로 분석하였다. 뿐만 아니라 4개의 시냅스를 지닌 2개의 혼돈 뉴런으로 이루어진 카오스 신경 회로망을 구성하여 시냅스 가중치에 따른 분기도 변화를 구하고 뉴럴 네트워크에서의 응용 가능성을 확인하였다. 한편 CMOS 집적회로로 구현된 혼돈 뉴런을 ±2.5V 전원, 10㎑의 클럭으로 구동시켜 단일 혼돈 뉴런 및 2개의 뉴런으로 이루어진 카오스 신경망에 대한 여러 동적 응답 특성을 측정하여 수치해석 결과와 비교, 분석하였다.

• Applied Microscopy
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• 제46권4호
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• pp.171-175
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• 2016

A distinctive neuronal network in the brain is believed to make us unique individuals. Electron microscopy is a valuable tool for examining ultrastructural characteristics of neurons, synapses, and subcellular organelles. A recent technological breakthrough in volume electron microscopy allows large-scale circuit reconstruction of the nervous system with unprecedented detail. Serial-section electron microscopy-previously the domain of specialists-became automated with the advent of innovative systems such as the focused ion beam and serial block-face scanning electron microscopes and the automated tape-collecting ultramicrotome. Further advances in microscopic design and instrumentation are also available, which allow the reconstruction of unprecedentedly large volumes of brain tissue at high speed. The recent introduction of correlative light and electron microscopy will help to identify specific neural circuits associated with behavioral characteristics and revolutionize our understanding of how the brain works.

• 한국ITS학회 논문지
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• 제11권4호
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• pp.63-69
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• 2012

본 논문에서는 용량성 지문센서의 회색조 이미지를 얻기 위한 새로운 회로를 제안하고 있다. 기존의 회로는 회색조 이미지를 얻기 위해 많은 칩 면적을 차지하는 DAC를 적용하거나 전력소모가 많고 전역 클럭을 적용하는 비휘발성 메모리에 적용되는 승압회로를 픽셀별로 적용하였다. 개선된 전하분할 방식의 용량성 지문센서 감지회로는 뉴런모스(vMOS) 기반의 DLC(down literal circuit) 회로와 단순화된 아날로그 MUX(multiplexor)를 적용하였다. 설계된 감지회로는 0.3V, $0.35{\mu}m$ CMOS공정을 적용하여 동작을 검증하였다. 제안된 회로는 기존의 비교기와 주변회로를 필요로하지 않으므로 단위 픽셀의 레이아웃 면적을 줄이고 이미지의 해상도를 향상 시킬 수 있다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.598-602
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• 2003

In this paper, we propose the method to control the position of LDM(Linear DC Motor) using vision system. The proposed method is composed of a vision system for position detecting, and main computer calculates PID control output which is deliver to 8051 actuator circuit in serial communication. To confirm the usefulness of the proposed method, we experimented about position control of a small size LDM using CCD camera which has a performance 30frames/sec as vision system.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.1188-1191
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• 2002

A number of studies have recently been published concerning neuron models and asynchronous neural networks. In the case of large-scale neural networks having neuron models, the neural network should be constructed using analog hardware, rather than by computer simulation via software, because of the limitation of the computational power, In this paper, we discuss the circuit structure of a synaptic section model having the spatio-temporal summation of inputs and utilizing CMOS processing.