• 한국HCI학회:학술대회논문집
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• 2007.02c
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• pp.322-325
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• 2007

Graphics processing unit (GPU) is used for a faster artificial neural network. It is used to implement the matrix multiplication of a neural network to enhance the time performance of a text detection system. Preliminary results produced a 20-fold performance enhancement using an ATI RADEON 9700 PRO board. The parallelism of a GPU is fully utilized by accumulating a lot of input feature vectors and weight vectors, then converting the many inner-product operations into one matrix operation. Further research areas include benchmarking the performance with various hardware and GPU-aware learning algorithms. (c) 2004 Pattern Recognition Society. Published by Elsevier Ltd. All rights reserved.

• ETRI Journal
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• v.44 no.5
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• pp.849-858
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• 2022

Dynamic voltage frequency scaling (DVFS) has been widely adopted for runtime power management of various processing units. In the case of neural processing units (NPUs), power management of neural network applications is required to adjust the frequency and voltage every layer to consider the power behavior and performance of each layer. Unfortunately, DVFS is inappropriate for layer-wise run-time power management of NPUs due to the long latency of voltage scaling compared with each layer execution time. Because the frequency scaling is fast enough to keep up with each layer, we propose a layerwise dynamic frequency scaling (DFS) technique for an NPU. Our proposed DFS exploits the highest frequency under the power limit of an NPU for each layer. To determine the highest allowable frequency, we build a power model to predict the power consumption of an NPU based on a real measurement on the fabricated NPU. Our evaluation results show that our proposed DFS improves frame per second (FPS) by 33% and saves energy by 14% on average, compared with DVFS.

• The Journal of the Convergence on Culture Technology
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• v.3 no.4
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• pp.171-175
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• 2017

Recently, Training of the convolutional neural network (CNN) entails many iterative computations. Therefore, a method of accelerating the training speed through parallel processing using the hardware specifications of GPGPU is actively researched. In this paper, the operations of the feature extraction unit and the classification unit are divided into blocks and threads of GPGPU and processed in parallel. Convolution and Pooling operations of the feature extraction unit are processed in parallel at once without sequentially processing. As a result, proposed method improved the training time about 314%.

• The Journal of Information Technology
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• v.4 no.3
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• pp.155-163
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• 2001

In this paper, we implemented sigmoid active function which make it difficult to design of the digital neuron networks. Therefore, we designed of the high speed processing of the sigmoid function in order to digital neural networks. we designed of the MAC(Multiplier and Accumulator) operation unit used residue number system without carry propagation for the high speed operation. we designed of MAC operation unit and sigmoid processing unit are proved that it could run of the high speed. On the simulation, the faster than 4.6ns on the each order, we expected that it adapted to the implementation of the high speed digital neural network.

• Journal of Electrical Engineering and Technology
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• v.5 no.3
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• pp.363-370
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• 2010

Load forecasting has always been essential to the operation and planning of power systems in deregulated electricity markets. Various methods have been proposed for load forecasting, and the neural network is one of the most widely accepted and used techniques. However, to obtain more accurate results, more information is needed as input variables, resulting in huge computational costs in the learning process. In this paper, to reduce training time in multi-layer perceptron-based short-term load forecasting, a graphics processing unit (GPU)-based computing method is introduced. The proposed approach is tested using the Korea electricity market historical demand data set. Results show that GPU-based computing greatly reduces computational costs.

• The Journal of Information Technology
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• v.2 no.2
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• pp.145-161
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• 1999

This paper proposes a high speed back propagation neural networks which uses the residue number system. making the high speed operation possible without carry propagation Consisting of MAC(Multiplication and Accumulation) operator unit using Residue number system and sigmoid function operator unit using Mixed Residue Conversion is designed, The Designed circuits are descripted by VHDL and synthesized by Compass tools. Result of simulations shows that critical path delay time is about 19nsec and the size can be reduced to 40% compared to the neural networks implemented by the real number operation unit. The proposed design circuits can be implemented in parallel distributed processing system with desired real time processing.

• Biomolecules & Therapeutics
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• v.26 no.2
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• pp.93-100
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• 2018

Carbon monoxide (CO) is a gaseous molecule produced from heme by heme oxygenase (HO). Endogenous CO production occurring at low concentrations is thought to have several useful biological roles. In mammals, especially humans, a proper neurovascular unit comprising endothelial cells, pericytes, astrocytes, microglia, and neurons is essential for the homeostasis and survival of the central nervous system (CNS). In addition, the regeneration of neurovascular systems from neural stem cells and endothelial precursor cells after CNS diseases is responsible for functional repair. This review focused on the possible role of CO/HO in the neurovascular unit in terms of neurogenesis, angiogenesis, and synaptic plasticity, ultimately leading to behavioral changes in CNS diseases. CO/HO may also enhance cellular networks among endothelial cells, pericytes, astrocytes, and neural stem cells. This review highlights the therapeutic effects of CO/HO on CNS diseases involved in neurogenesis, synaptic plasticity, and angiogenesis. Moreover, the cellular mechanisms and interactions by which CO/HO are exploited for disease prevention and their therapeutic applications in traumatic brain injury, Alzheimer's disease, and stroke are also discussed.

• Journal of the Korean Society of Visualization
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• v.19 no.1
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• pp.57-61
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• 2021

In order to determine erythrocyte sedimentation rate (ESR) indicating acute phase inflammation, a Westergren method has been widely used because it is cheap and easy to be implemented. However, the Westergren method requires quite a long time for 1 hour. In this study, a gated recurrent unit (GRU) neural network was used to reduce measurement time of ESR evaluation. The sedimentation sequences of the erythrocytes were acquired by the camera and data processed through image processing were used as an input data into the neural network models. The performance of a proposed models was evaluated based on mean absolute error. The results show that GRU model provides best accurate prediction than others within 30 minutes.

• 전자공학회논문지 IE
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• v.44 no.3
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• pp.12-22
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• 2007

In this paper, we designed of the high speed digital neuron processor in order to digital neural networks. we designed of the MAC(Multiplier and Accumulator) operation unit used residue number system without carry propagation for the high speed operation. and we implemented sigmoid active function which make it difficult to design neuron processor. The Designed circuits are descripted by VHDL and synthesized by Compass tools. we designed of MAC operation unit and sigmoid processing unit are proved that it could run time 19.6 nsec on the simulation and decreased to hardware size about 50%, each order. Designed digital neuron processor can be implementation in parallel distributed processing system with desired real time processing, In this paper.

• IEMEK Journal of Embedded Systems and Applications
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• v.17 no.4
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• pp.217-228
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• 2022

Currently, there are increasing demands for applying deep neural networks (DNNs) in the embedded domain such as classification and object detection. The DNN processing in embedded domain often requires custom hardware such as NPU for acceleration due to the constraints in power, performance, and area. Processing DNN models requires a large amount of data, and its seamless transfer to NPU is crucial for performance. In this paper, we developed a cycle-accurate NPU simulator to evaluate diverse NPU microarchitectures. In addition, we propose a novel technique for reducing the number of memory accesses when processing convolutional layers in convolutional neural networks (CNNs) on the NPU. The main idea is to reuse data with memory interleaving, which recycles the overlapping data between previous and current input windows. Data memory interleaving makes it possible to quickly read consecutive data in unaligned locations. We implemented the proposed technique to the cycle-accurate NPU simulator and measured the performance with LeNet-5, VGGNet-16, and ResNet-50. The experiment shows up to 2.08x speedup in processing one convolutional layer, compared to the baseline.