• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.7
• /
• pp.131-139
• /
• 2013

To overcome the limitations in performance and power consumption of traditional electrical interconnection based network-on-chips (NoCs), a hybrid optical network-on-chip (HONoC) architecture using optical interconnects is emerging. However, the HONoC architecture should use circuit-switching scheme owing to the overhead by optical devices, which worsens the latency unfairness problem caused by frequent path collisions. This resultingly exert a bad influence in overall performance of the system. In this paper, we propose a new task mapping algorithm for optimizing latency by reducing path collisions. The proposed algorithm allocates a task to a certain processing element (PE) for the purpose of minimizing path collisions and worst case latencies. Compared to the random mapping technique and the bandwidth-constrained mapping technique, simulation results show the reduction in latency by 43% and 61% in average for each $4{\times}4$ and $8{\times}8$ mesh topology, respectively.

• Journal of Institute of Control, Robotics and Systems
• /
• v.5 no.8
• /
• pp.995-1000
• /
• 1999

This paper presents a optic system and a visual inspection algorithm looking for solder joint defects of J-lead chip which are more integrate and smaller than ones with Gull-wing on PCBs(Printed Circuit Boards). The visual inspection system is composed of three sections : host PC, imaging and driving parts. The host PC part controls the inspection devices and executes the inspection algorithm. The imaging part acquires and processes image data. And the driving part controls XY-table for automatic inspection. In this paper, the most important five features are extracted from input images to categorize four classes of solder joint defects in the case of J-lead chip and utilized to a back-propagation network for classification. Consequently, good accuracy of classification performance and effectiveness of chosen five features are examined by experiment using proposed inspection algorithm.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2007.11a
• /
• pp.457-458
• /
• 2007

We investigated a resistor network model for the horizontal AlInGaN LED. Adding the proposed current density dependent relative quantum efficiency, the power simulation can be also obtained. Comparing the simulation and the measurement results for the LED with the size of $350{\mu}m$, the model is reasonable to simulate the forward voltage and the light output power. Using this model we investigated the optimization of the position and the number of the finger electrodes in a given chip area. It shows that the center disposition of the p-finger electrode in p-area is optimal for the voltage and best for the power. And the minimum number of the n-finger electrodes is best for the power.

• Proceedings of the Korean Society of Applied Pharmacology
• /
• 2002.07a
• /
• pp.73-78
• /
• 2002

Microfluidic lab-on-a-chip (LOC) systems have enabled a new generation ofassay technologies in chemical and biomedical sciences. Caliper's microfluidic LOC systems contain a network of microscopic channels through which fluids and chemical are moved in order to perform experiments. The main advantages of these continuous-flow devices are integration and automation of multiple steps in complex analytical procedures to improve the reproducibility of the results, and eliminated the manual labor, time and pipetting errors involved in analyses. The present talk is devoted to give a brief introduction of microfluidic basics and to present in applying continuous-flow microchips to drug screening with model enzyme assays.

• ETRI Journal
• /
• v.38 no.6
• /
• pp.1240-1249
• /
• 2016

With the number of IP cores in a multicore system-on-chip increasing to up to tens or hundreds, the role of on-chip interconnection networks is vital. We propose a networks-on-chip-style bus network as a compromise and redefine the exploration problem to find the best IP tiling patterns and communication path combinations. Before solving the problem, we estimate the time complexity and validate the infeasibility of the solution. To reduce the time complexity, we propose two fast exploration algorithms and develop a program to implement these algorithms. The program is executed for several experiments, and the exploration time is reduced to approximately 1/22 and 7/1,200 at the first and second steps of the exploration process, respectively. However, as a trade-off for the time saving, the time cost (TC) of the searched architecture is increased to up to 4.7% and 11.2%, respectively, at each step compared with that of the architecture obtained through full-case exploration. The reduction ratio can be decreased to 1/4,000 by simultaneously applying both the algorithms even though the resulting TC is increased to up to 13.1% when compared with that obtained through full-case exploration.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.4
• /
• pp.117-123
• /
• 2008

In this paper, we propose a novel ant colony optimization(ACO)-based application core ma ins method for implementing network-on-chip(NoC)-based systems-on-chip(SoCs). The proposed method efficiently put application cores to a mesh-type NoC satisfying a given design objective, the network latency. Experimental results using a functional circuit including 12 cores show that the proposed algorithm can produce near optimal mapping results within a second.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.61 no.2
• /
• pp.347-353
• /
• 2012

In this paper, authors will develop the quick and precise remote controller of automatic fire detection equipment (P-type one-class receiver) based on information communication technology (IT). The remote controller detects the fire and disaster in the building automatically and quickly and then activates the facilities to extinguish the fire and disaster, monitoring such situation in a real time through wire-wireless communication network. The proposed remote controller is applied a programmable logic device (PLD) micom. of one-chip type which is small size and lightweight and also has highly sensitive-precise reliabilities. The one-chip type PLD micom. analyzes digital signals from sensors, then activates fire extinguishing facilities for alarm and rapid suppression in a case of fire and disaster. The detected data is also transferred to a remote situation room through wire-wireless network of RS232c and bluetooth communication, and then the situation room sends an emergency alarm signal. The automatic fire detection equipment (AFDE) based on IT will minimize the life and wealth loss while prevents fire and disaster.

• IEIE Transactions on Smart Processing and Computing
• /
• v.5 no.2
• /
• pp.71-76
• /
• 2016

A controller area network (CAN) receiver measures differential voltage on a bus to determine the bus level. Since 3.3V transceivers generate the same differential voltage as 5V transceivers (usually ${\geq}1.5V$), all transceivers on the bus (regardless of supply voltage) can decipher the message. In fact, the other transceivers cannot even determine or show that there is anything different about the differential voltage levels. A new CMOS RC oscillator insensitive supply voltage for clock generation in a CAN transceiver was fabricated and tested to compensate for this drawback in CAN communication. The system consists of a symmetrical circuit for voltage and current switches, two capacitors, two comparators, and an RS flip-flop. The operational principle is similar to a bistable multivibrator but the oscillation frequency can also be controlled via a bias current and reference voltage. The chip test experimental results show that oscillation frequency and power dissipation are 500 kHz and 5.48 mW, respectively at a supply voltage of 3.3 V. The chip, chip area is $0.021mm^2$, is fabricated with $0.18{\mu}m$ CMOS technology from SK hynix.

• Journal of electromagnetic engineering and science
• /
• v.11 no.4
• /
• pp.282-289
• /
• 2011

GHz electromagnetic interference (EMI) characteristics are analyzed for a 3dimensional (3D) stacked chip power distribution network (PDN) with through silicon via (TSV) connections. The EMI problem is mostly raised by P/G (power/ground) noise due to high switching current magnitudes and high PDN impedances. The 3D stacked chip PDN is decomposed into P/G TSVs and vertically stacked capacitive chip PDNs. The TSV inductances combine with the chip PDN capacitances produce resonances and increase the PDN impedance level in the GHz frequency range. These effects depend on stacking configurations and P/G TSV designs and are analyzed using the P/G TSV model and chip PDN model. When a small size chip PDN and a large size chip PDN are stacked, the small one's impedance is more seriously affected by TSV effects and shows higher levels. As a P/G TSV location is moved to a corner of the chip PDNs, larger PDN impedances appear. When P/G TSV numbers are enlarged, the TSV effects push the resonances to a higher frequency range. As a small size chip PDN is located closer to the center of a large size chip PDN, the TSV effects are enhanced.

• 제어로봇시스템학회:학술대회논문집
• /
• 2002.10a
• /
• pp.89.4-89
• /
• 2002

$\textbullet$ Field Programmable Gate Array $\textbullet$ flexible hardware $\textbullet$ neural network $\textbullet$ determinism learning $\textbullet$ multi-valued logic $\textbullet$ disjunctive normal form $\textbullet$ multi-dimensional exclusive OR