• 한국정밀공학회지
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• 제28권2호
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• pp.176-184
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• 2011

As modern megalopolises become more complex and huge, convenience and safety of citizens are main components for a welfare state. In order to make safe society, telemetrics technology, which remotely measures the information of target system using electronic devices, is an essential component. In general, telemetrics technology consists of USN (ubiquitous sensor network) based on a wireless network, smart sensor, and SoC (system on chip). In the smart sensor technology, the following two problems should be overcome. Firstly, because it is very difficult for transducer manufacturers to develop smart sensors that support all the existing network protocols, the smart sensor must be independent of the type of networking protocols. Secondly, smart sensors should be modular so that a faulty sensor element can be replaced without replacing healthy communication element. To solve these problems, this paper investigates the feasibility of an IEEE 1451 based ZigBee smart sensor system. More specifically, a smart sensor for large network coverage has been developed using ZigBee for active telemetrics.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.1296-1299
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• 2002

We implemented a CD signal processor operated on a CAV 48-speed CD-ROM drive into a VLSI. The CD signal processor is a mixed mode monolithic IC including servo-processor, data recovery, data-processor, and I-bit DAC. For servo signal processing, we included a DSP core, while, for CAV mode playback, we adopted a PLL with a wide recovery range. Data processor (DP) was designed to meet the yellow book specification.［2］So, the DP block consists of EFM demodulator, C1/C2 ECC block, audio processor and a block transferring data to an ATAPI chip. A modified Euclid's algorithm was used as a key equation solver for the ECC block To achieve the high-speed decoding, the RS decoder is operated by a pipelined method. Audio playability is increased by playing a CD-DA disc at the speed of 12X or 16X. For this, subcode sync and data are processed in the same way as main data processing. The overall performance of IC is verified by measuring a transfer rate from the innermost area of disc to the outermost area. At 48-speed, the operating frequency is 210 ㎒, and this chip is fabricated by 0.35 um STD90 cell library of Samsung Electronics.

• ETRI Journal
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• 제29권4호
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• pp.421-429
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• 2007

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

• 한국음향학회지
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• 제20권3호
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• pp.83-90
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• 2001

기존의 탄성표면파 듀플렉서 필터는 1/4 파장 정합선로를 이용한 격리회로를 이용하기 때문에 패키지 상에 스트립 라인을 구성하는 제작상의 어려움이 있다. 송수신 필터와 격리회로를 따로 제작하여 조립하기 때문에 제작공정 또한 복잡하다. 본 연구에서는 격리회로가 송신용, 수신용 필터와 함께 하나의 단일 칩 위에 위치할 수 있는 새로운 형태의 탄성표면파 듀플렉서 필터를 설계하였다. 이러한 형태의 듀플렉서를 구성하기 위하여, 개별 탄성표면파 사다리형 필터와 집중소자인 인덕터와 캐패시터로 구성되는 격리회로망을 설계하였고, 듀플렉서의 전체 성능을 최적화할 수 있는 적절한 목표함수를 세워, 이를 비선형 다차원 최소화 방법을 통하여 최적화하였다. 그 결과 상용제품보다 더 우수한 성능이 구현됨을 확인하였다.

• Progress in Superconductivity
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• 제4권1호
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• pp.74-79
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• 2002

High-speed probe made to test single flux quantum(SFQ) circuits was comprised of semi-rigid coaxial cables and microstrip lines. The impedance was set at 50 $\Omega$to carry high-speed signals without much loss. To do performance test of high-speed probe, we have attempted to fabricate a test chip which has a coplanar waveguide(CPW) structure. Electromagnetic simulation was done to optimize the dimension of CPW so that the CPW structure has an impedance of 50$\Omega$, matching in impedance with the probe. We also used the simulation to investigate the effect of the width of signal line and the gap between signal line and ground plane to the characteristics of CPW structure. We fabricated the CPW structure with a gold film deposited on Si wafer whose resistivity was above $1.5\times$10$_4$$\Omega$.cm. The magnitudes of S／sub 21／ of CPW at 6 ㎓ in simulations and in the actual measurements done with a network analyzer were: -0.1 ㏈ and -0.33 ㏈ (type A),-0.2 ㏈ and -0.48 ㏈ (type B), respectively. Using the test chip, we have successfully tested the performance of high-speed probe made for SFQ circuits. The probe showed the good performance overthe bandwidth of 10 ㎓.

• 한국정보처리학회논문지
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• 제2권3호
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• pp.433-442
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• 1995

시간 복잡도가 O(Ν)인 고집적 회로(VLSI)의 병렬 정렬기 설계에 관한 논문이다. 발표된 빠른 VLSI 정렬 알고리즘은 Ν개의 데이타를 정렬하기 위해 O(log Ν)시간 복 잡도를 가지고 있다. 그러나 이러한 알고리즘은 입출력 시간을 고려하지 않고, 복잡 한 네트워크 구조를 가지므로 확장이나 실용화하기 힘들다. 입출력 시간이 포함된 병 렬 정렬 알고리즘들의 칩면적과 시간 복잡도를 분석한 후 가장 효과적인 rebound sort 이론을 확장하여 VLSI로 구현한다. 이 리바운드 정렬기는 파이프라인으로 구성하여 O(Ν)의 시간 복잡도를 가지며 한 개의 칩에 8개의 16비트 레코드를 정렬할 수 있다. 그리고 이 정렬 칩은 확장성을 가지고 있어 수직으로 연결할 경우 8개 이상의 레코드 를 정렬할 수 있다.

• Journal of information and communication convergence engineering
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• 제8권2호
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• pp.219-222
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• 2010

An ubiquitous sensor network (USN) system to monitor the bio information and the emergency of the elderly in the silver town is presented. The USN system consists of the sensor node platforms based on MCU of Atmage128L and RF Chip of CC2420 satisfying IEEE 802.15.4, which includes the bios sensor module such as the electrocardiogram (ECG) sensor and the temperature sensor. Additionally, when an emergency of the elderly is occurred in the silver town, the routing algorithm suitable to find and inform the location of the elderly is proposed, and the proposed routing algorithm is applied to the USN. To collect and manage the ECG data at the PC connected to the sink node, LabView software is used. The bio information and the emergency of the elderly can also be monitored at the client PC by TCP/IP networks in the USN system.

• 대한임베디드공학회논문지
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• 제7권6호
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• pp.339-343
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• 2012

Security and monitoring system has many applications and commonly used for detection, warning, alarm, etc. As the networking technology advances, user requirements are getting higher. An intelligent and cooperative surveillance system is proposed to meet current user demands and improve the performance. This paper focuses on the implementation issue for the embedded intelligent surveillance system. To cover wide area cooperative function is implemented and connected by wireless sensor network technology. Also to improve the performance lots of sensors are employed into the surveillance system to reduce the error but improve the detection probability. The proposed surveillance system is composed of vision sensor (camera), mic array sensor, PIR sensor, etc. Between the sensors, data is transferred by IEEE 802.11s or Zigbee protocol. We deployed a private network for the sensors and multiple gateways for better data throughput. The developed system is targeted to the traffic accident detection and alarm. However, its application can be easily changed to others by just changing software algorithm in a DSP chip.

• 한국통신학회논문지
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• 제25권10A호
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• pp.1529-1539
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• 2000

이동 통신 망에서 초기 호 설정 과정에 필요한 액세스 채널의 접속은 시스템의 성능 및 용량과 밀접한 관련이 있다. 이 논문에서는 IS-95 CDMA 표준에 따른 액세스 채널의 동작 및 구조를 설명하고 관련된 시스템 패러미터 를 소개한다. 분석을 통하여, 기지국의 반경, 최대 재전송 횟수, 엑세스 채널과 페이징 채널의 메시지 에러율에 따른 액세스 채널이 가질 수 있는 여러가지 성능 통계량을 산출하였다. 동일한 슬롯에 2개 이상의 전송이 발생하면 충돌로 간주하는 Slotted aloha 모델에 비해, 동일한 슬롯에서도 1 PN chip 이상의 간격이 있다면 성공적인 도착으로 간주하는 IS-95 CDMA의 throuhput 이 훨씬 뛰어남을 알 수 있었고, 주어진 호 차단율에 따른 기지국의 적정 트래픽 채널 수를 유도할 수 있는 기준을 제시할 수 있었다.

• ETRI Journal
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• 제28권4호
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• pp.475-485
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• 2006

Network-on-chip (NoC) is an emerging design paradigm intended to cope with future systems-on-chips (SoCs) containing numerous built-in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC-based SoCs. Among the existing test issues for NoC-based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC-based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC-based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC'02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC-based SoCs.