• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.131.1-131
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• 2001

At the present time, multimedia chip, internet application, and network equipment is designed by using ARM core. Because it has a good debugging, software compiler and needed low power. We must process a data coding to send a multimedia data by real time. So need to connect software and hardware algorithm. In this research, We design interface for ARM9/AMBA based board using VHDL for these function implementation. The board is used the ARM company´s ARM940T for software function implementation and Xilinx company´s Virtex E2000 for hardware function algorithm. The various hardware algorithm (ME,ME,DCT) block for performance can be implemented on this system.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.149-152
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• 2002

In this paper, We have designed an internal chip type-ceramic antenna and diplexer for dual-band handset applications. for increasing bandwidth, antennas used a meander line structure with L, C matching network. The designed diplexer is based on the multi-layered structure for the purpose of the LTCC applications. We have given a notch using resonator for elevated attenuation characteristics.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1992.10a
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• pp.293-297
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• 1992

For the computerized monitoring and diagnosis of the undesirable chip chatter which are major obstacles to FMS, a pattern recognition system based on multi-layer perception neural network is developed and the performance of the system is experimentally evaluated. Experimental results show that recognition of the two class state of normal or abnormal cutting gives satisfactory results with success rate of 81`91%. Therefore, the proposed system has possibility for use in monitoring and diagnosis of automatic manufacturing system

• Journal of KIISE:Software and Applications
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• v.29 no.11
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• pp.775-784
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• 2002

Microarray data, obtained from DNA chip technologies, is the measurement of the expression level of thousands of genes in cells or tissues. It is used for gene function prediction or cancer diagnosis based on gene expression patterns. Among diverse methods for data analysis, the Bayesian network represents the relationships among data attributes in the form of a graph structure. This property enables us to discover various relations among genes and the characteristics of the tissue (e.g., the cancer type) through microarray data analysis. However, most of the present microarray data sets are so sparse that it is difficult to apply general analysis methods, including Bayesian networks, directly. In this paper, we harness an efficient structural learning algorithm and data dimensionality reduction in order to analyze microarray data using Bayesian networks. The proposed method was applied to the analysis of real microarray data, i.e., the NC160 data set. And its usefulness was evaluated based on the accuracy of the teamed Bayesian networks on representing the known biological facts.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.558-560
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• 2009

Ad hoc could be very important in the location-based technology, much research could work underway in these days. In this paper, the property of based on RSSI (Received signal strength indicator) could extract information. A distance of self-made nodes testing were implemented for an each other between given nodes. A special purpose UoC (ubiquitous of System On Chip) system was developed in this paper. This system could provide a function of RSSI property for location information experiments. This attribute information could make possible LBS (Location-Based System) experiment for ranging technique in this development system. The experiment results could show a possibility performance delivery ratio and the number of hops. This given performance of the location information could be used to acquire a ranging technique in large number of nodes network system.

• The Korean Journal of Applied Statistics
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• v.29 no.6
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• pp.1117-1128
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• 2016

In genetic association studies with high-dimensional genomic data, regularization procedures based on penalized likelihood are often applied to identify genes or genetic regions associated with diseases or traits. A network-based regularization procedure can utilize biological network information (such as genetic pathways and signaling pathways in genetic association studies) with an outstanding selection performance over other regularization procedures such as lasso and elastic-net. However, network-based regularization has a limitation because cannot be applied to high-dimension genomic data with a group structure. In this article, we propose to combine data dimension reduction techniques such as principal component analysis and a partial least square into network-based regularization for the analysis of high-dimensional genomic data with a group structure. The selection performance of the proposed method was evaluated by extensive simulation studies. The proposed method was also applied to real DNA methylation data generated from Illumina Innium HumanMethylation27K BeadChip, where methylation beta values of around 20,000 CpG sites over 12,770 genes were compared between 123 ovarian cancer patients and 152 healthy controls. This analysis was also able to indicate a few cancer-related genes.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.123-126
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• 2004

Demands on dealing with multimedia data through the network have been increased, and networking multimedia devices require processing, transmitting , and receiving the digital data. In order to implement the network for high performance and low cost, we may have to integrate the dedicated hardware into a system on a chip by spending an extra amount of silicon resource. In this paper, we describe hardware implementation of TCP/IP protocol stack which is now popular to connect multiple PCs and peripherals by means of networks. For evaluation we used ALTERA APEX 20K600EBC652 FPGA with 600,000 gates. The operating frequency is estimated 29.9MHz and it used area of $26\%$.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.391-393
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• 2004

For performance and stability of a synchronized system, we need an efficient Clock Tree Synthesis(CTS) methodology to design clock distribution networks. In a system-on-a-chip(SOC) design environment, CTS effectively distributes clock signals from clock sources to synchronized points on layout design. In this paper, we suggest the pre-layout analysis of the clock network including gated clock, multiple clock, and test mode CTS optimization. This analysis can help to avoid design failure with potential CTS problems from logic designers and supply layout constraints so as to get an optimal clock distribution network. Our new design flow including pre-layout CTS analysis and structural violation checking also contributes to reduce design time significantly.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.2266-2270
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• 2005

In this paper, an internet based control application for dynamical systems is implemented. This implementation is maily targeted for the part of advanced control education. Intelligent control algorithms are implemented in a PC so that a client can remotely access the PC to control a dynamical system through the internet. Neural network is used as an on-line intelligent controller. To have on-line learning and control capability, the reference compensation technique is implemented as intelligent control hardware of combining a DSP board and an FPGA chip. GUIs for a user are also developed for the user's convenience. Actual experiments of motion control of a DC motor have been conducted to show the performance of the intelligent control though the internet and the feasibility of advanced control education.

• Journal of the Korea Society of Computer and Information
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• v.14 no.10
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• pp.23-29
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• 2009

This paper presents the development of embedded network educational system. This is an educational equipment which enables user to have training over Network Configuration and Embedded network programming practice on Internet environment. The network education system is developed on embedded environment. based on using ethernet interface. On the development environment. PAX255 VLSI chip is used for the processor, the ADSv1.2 for debugging, uC/OS276 for RTOS. The system software was developed using C language. The ping program provided an educational environment for the student to compile and load it to run after doing practice of demonstration behavior. Afterwards programming procedure starts the step-by-step training just like the demonstration function. In other words, programming method how to design the procedure of ARP operation and ICMP operation is explained.