• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.7-16
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• 2007

In this paper, we introduce a new design environment for efficient multiprocessor system-on-chip design space exploration. The design environment takes a process network model as input system specification. The process network model has been widely used for modeling signal processing applications because of its excellent modeling power. However, it has limitation in predictability, which could cause severe problem for real time systems. This paper proposes a new approach that enables static analysis of a process network model by converting it to a hierarchical synchronous dataflow model. For efficient design space exploration in the early design step, mapping application to target architectures has been a crucial part for finding better solution. In this paper, we propose an efficient mapping algorithm. Our mapping algorithm supports both single bus architecture and multiple bus architecture. In the experiments, we show that the automatic conversion approach of the process network model for static analysis is performed successfully for several signal processing applications, and show the effectiveness of our mapping algorithm by comparing it with previous approaches.

• IMMUNE NETWORK
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• v.6 no.3
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• pp.128-137
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• 2006

Background: Apoptosis is a physiologic phenomenon involved in development, elimination of damaged cells, and maintenance of cell homeostasis. Deregulation of apoptosis may cause diseases, such as cancers, immune diseases, and neurodegenerative disorders. The mouse myeloma cell P3-X63-Ag8.653 (v653) is an HGPRT deficient $(HGPRT^-)$ mutant strain. High dependency on de novo transcription and translation of aminopterin induced apoptosis of this cell seems to be an ideal experimental system for searching apoptosis-induced genes. Methods & Results: For searching apoptosis-related genes we carried out GE-array (dot blot), Affymetrix GeneChip analysis, Northern analysis and differential display-PCR techniques. The chip data were analyzed with three different programs. 66 genes were selected through Affymetrix GeneChip analyses. All genes selected were classified into 8 groups according to their known functions. They were Genes of 1) Cell growth/maintenance/death/enzyme, 2) Cell cycle, 3) Chaperone, 4) Cancer/disease-related genes, 5) Mitochondria, 6) Membrane protein/signal transduction, 7) Nuclear protein/nucleic acid binding/transcription binding and 8) Translation factor. Among these groups number of genes were the largest in the genes of cell growth/maintenance/death/enzyme. Expression signals of most of all groups were peaked at 3 hour of apoptosis except genes of Nuclear protein/nucleic acid binding/transcription factor which showed maximum signal at 1 hour. Conclusion: This study showed induction of wide range of proapoptotic factors which accelerate cell death at various stage of cell death. In addition apoptosis studied in this research can be classified as a type 2 which involves cytochrome c and caspase 9 especially in early stages of death. But It also has progressed to type 1 in late stage of the death process.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.5
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• pp.592-597
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• 2012

In this paper, a new small chip antenna for Wi-Fi application of the mobile handset is proposed. To miniaturize the chip antenna, the proposed antenna is designed to have the backside ground. The proposed antenna has S-shaped structure, which is designed on the LCP(Liquid Crystal Polymer) with ${\varepsilon}_r$=3.5. The size of the proposed antenna is $6.0mm{\times}2.5mm{\times}1.2mm$. The measured impedance bandwidth under a voltage standing wave ratio (VSWR) of 2 was 300 MHz(fractional bandwidth: 12.2 % 2.3~2.6 GHz), and peak gain is 1.42 dBi. The proposed antenna was designed using CST Microwave Studio commercial software tool. And the fabricated antenna is measured using a network analyzer and in anechoic chamber.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.10
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• pp.1427-1434
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• 2013

In this paper, triple band mobile chip antenna for DCS(1.71~1.88GHz) / PCS(1.75~1.87GHz) / UPCS(1.85~1.99GHz) on PCB Layout is designed. To analyze the characteristics of the designed antenna, we designed and measured Single, Dual, Triple Band antenna. The designed antenna was fabricated and measured using vector network analyzer in LTK(Laird Technologies Korea). Triple and wide band characteristic could be realized the measured bandwidth(V.S.W.R<2.0) of designed antenna operated in the band of 1.71GHz~1.99GHz. This antenna has a small size of about $19mm{\times}4mm{\times}1.6mm$, narrow bandwidth which is a defect of chip antenna is improved. And its experimental results were a good agreement with simulation performance.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.96-101
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• 2015

This paper describes a design and implementation of the NFC bridge chip which performs interface between kinds of devices and mobile phones including NFC controller through NFC communication. The NFC bridge chip consists of the digital part and the analog part which are based on NFC Forum standard. Therefore the chip treats RF signals and then transforms the signal to digital data, so it can interface kinds of devices with the digital data. Especially the chip is able to detect RF signals and then wake up the host processor of a device. The wakeup function dramatically decreases the power consumption of the device. The carrier frequency is 13.56MHz, and the data rate is up to 424kbps. The chip has been fabricated with SMIC 180nm mixed-mode technology. Additionally an NFC bridge chip application to the blood glucose measurement system is described for an application example.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.5
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• pp.349-357
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• 2016

The era of the Internet of Things (IoT) is upon us. In this era, minimizing power consumption becomes a primary concern for system-on-chip designers. While traditional power minimization and dynamic power management (DPM) techniques have been heavily explored to improve the power efficiency of devices inside very large-scale integration (VLSI) platforms, there is one critical factor that is often overlooked, which is the power conversion efficiency of a power delivery network (PDN). This paper is a tutorial that focuses on the power conversion efficiency of the PDN, and introduces novel methods to improve it. Circuit-, architecture-, and system-level approaches are presented to optimize PDN designs, while case studies for three different VSLI platforms validate the efficacy of the introduced approaches.

• The KIPS Transactions:PartB
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• v.9B no.4
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• pp.429-436
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• 2002

In order to apply the artificial neural network to the practical application, it is needed to implement it with the hardware system. It is most promising to make it with the hybrid VLSI among various possible technologies. When we Implement a trained network into the hybrid neuro-chips, it is to be performed the process of the quantization on its neuron outputs and its weights. Unfortunately this process cause the network's outputs to be distorted from the original trained outputs. In this paper we analysed in detail the statistical characteristics of the distortion. The analysis implies that the network is to be trained using the normalized input patterns and finally into the solution with the small weights to reduce the distortion of the network's outputs. We performed the experiment on an application in the time series prediction area to investigate the effectiveness of the results of the analysis. The experiment showed that the network by our method has more smaller distortion compared with the regular network.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2006.05a
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• pp.125-129
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• 2006

By advent of NNC(Neural Network Chip), it is possible that process in parallel and discern the importance of signal with learning oneself by experience in external signal. So, the design of general purpose operation unit using VHDL(VHSIC Hardware Description Language) on the existing FPGA(Field Programmable Gate Array) can replaced EN(Expert Network) and learning algorithm. Also, neural network operation unit is possible various operation using learning of NN(Neural Network). This paper present general purpose operation unit using hierarchical structure of EN. EN of presented structure learn from logical gate which constitute a operation unit, it relocated several layer. The overall structure is hierarchical using a module, it has generality more than FPGA operation unit.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.1
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• pp.92-98
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• 2019

In this paper, we propose a deep learning system based on morphological neural network(MNN). The deep learning layers are morphological operation layer, pooling layer, ReLU layer, and the fully connected layer. The operations used in morphological layer are erosion, dilation, and edge detection, etc. Unlike CNN, the number of hidden layers and kernels applied to each layer is limited in MNN. Because of the reduction of processing time and utility of VLSI chip design, it is possible to apply MNN to various mobile embedded systems. MNN performs the edge and shape detection operations with a limited number of kernels. Through experiments using database images, it is confirmed that MNN can be used as a deep learning system and its performance.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.145-148
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• 2002

In a network communication process, cryptographic algorithms play important role for secure process. This paper presents a new system architecture named "DCCS." This system can handle flexible operations of both cryptographic algorithms and the keys. For experimental evaluation, two representative cryptographic algorithms DES and Triple-DES are designed and implemented into an FPGA chip on the SEBSW-1. Then the developed board is confirmed to change its cryptographic algorithms dynamically. Also its throughput confirmed the ability of the real-time net-work use of the designed system.