• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.670-673
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• 2002

This paper proposes a digital algorithm for gray-scale/color image segmentation of real-time video signals and a cell-network-based implementation architecture in state-of-the-art CMOS technology. Through extrapolation of design and simulation results we predict that about 300$\times$300 pixels can be integrated on a chip at 100nm CMOS technology, realizing very high-speed segmentation at about 1600sec per color image. Consequently real-time color-video segmentation will become possible in near future.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.64 no.4
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• pp.321-326
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• 2015

Smart metering is one of the most implementable internet-of-thing service. In order to implement the smart metering, a wireless communication network should be newly designed and evaluated so as to satisfy quality-of-service of smart metering. In this paper, we consider a wireless network for the smart metering implemented with multi-purpose wireless chips and channel coding-functioned micro controllers. Especially, channel coding is newly adopted to improve successful frame transmission probability. Based on the successful frame transmission probability, average transmission delay and delay violation probability are analyzed. Using the analytical results, service coverage expansion is evaluated. Through the delay analysis, service feasibility can be verified. According to our results, channel coding needs not to be utilized to improve the delay performance if the smart metering service coverage is several tens of meters. However, if more coverage is required, chanel coding adoption definitely reduces the delay time and improve the service feasibility.

• Journal of the Korea Society of Computer and Information
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• v.14 no.7
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• pp.65-72
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• 2009

This paper proposed VCR cryptographic algorithm that adapted in TCP/IP protocol architecture and wire/wireless communication network environments. we implemented by hardware chip level because proposed VCR cryptographic algorithm perform scalable & reconfigurable operations into the security system. Proposed VCR cryptographic algorithm strengthens security vulnerability of TCP/IP protocol and is very profitable real-time processing and encipherment of high-capacity data and multi-user communication because there is important purpose to keep security about many user as that have variable round numbers function in network environments.

• Journal of Korea Multimedia Society
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• v.17 no.3
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• pp.324-332
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• 2014

This paper presents a programmable System-On-a-chip for various embedded applications that need Neural Network computations. The system is fully implemented into Field-Programmable Gate Array (FPGA) based prototyping platform. The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using real image processing applications, such as optical character recognition (OCR) system.

• Journal of Electrical Engineering and information Science
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• v.1 no.1
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• pp.98-107
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• 1996

In this paper, we propose a scheme that maps the time-delay neural network (TDNN) into the neurocomputer called EMIND-II which has the wavefront toroidal mesh-array structure. This neurocomputer is scalable, consists of many timeshared virtual neurons, is equipped with programmable on-chip learning, and is versatile for building many types of neural networks. Also we define the programming model of this array and derive the parallel algorithms about TDNN for the proposed neurocomputer EMIND-II. In addition, the computational complexities for the parallel and serial algorithms are compared. Finally, we introduce an application of this neurocomputer to word recognition.

• Industrial Engineering and Management Systems
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• v.9 no.3
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• pp.227-241
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• 2010

A memory module industry's supply chain usually consists of multiple manufacturing sites and multiple distribution centers. In order to fulfill the variety of demands from downstream customers, production planners need not only to decide the order allocation among multiple manufacturing sites but also to consider memory module industrial characteristics and supply chain constraints, such as multiple material substitution relationships, capacity, and transportation lead time, fluctuation of component purchasing prices and available supply quantities of critical materials (e.g., DRAM, chip), based on human experience. In this research, a directed graph-based supply network planning (DGSNP) model is developed for memory module industry. In addition to multi-site order allocation, the DGSNP model explicitly considers production planning for each manufacturing site, and purchasing planning from each supplier. First, the research formulates the supply network's structure and constraints in a directed-graph form. Then, a proposed genetic algorithm (GA) solves the matrix form which is transformed from the directed-graph model. Finally, the final matrix, with a calculated maximum profit, can be transformed back to a directed-graph based supply network plan as a reference for planners. The results of the illustrative experiments show that the DGSNP model, compared to current memory module industry practices, determines a convincing supply network planning solution, as measured by total profit.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.1
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• pp.296-308
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• 2015

Advanced Encryption Standard (AES) is widely used for protecting wireless sensor network (WSN). At the Workshop on Cryptographic Hardware and Embedded Systems (CHES) 2012, G$\acute{e}$rard et al. proposed an optimized collision attack and break a practical implementation of AES. However, the attack needs at least 256 averaged power traces and has a high computational complexity because of its byte wise operation. In this paper, we propose a novel double sieve collision attack based on bitwise collision detection, and an improved version with an error-tolerant mechanism. Practical attacks are successfully conducted on a software implementation of AES in a low-power chip which can be used in wireless sensor node. Simulation results show that our attack needs 90% less time than the work published by G$\acute{e}$rard et al. to reach a success rate of 0.9.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.4
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• pp.216-224
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• 2009

The endless scaling down of the semiconductor process made the impact of the power network noise on the performance of the state-of-the-art chip a serious design problem. This paper compares the performances of two popular circuit reduction approaches used to improve the efficiency of power network noise analysis: moment matching-based model order reduction (MOR) and node elimination-based MOR. As the benchmarks, we chose PRIMA and R2Power as the matching-based MOR and the node elimination-based MOR. Experimental results indicate that the accuracy, efficiency, and memory requirement of both methods very strongly depend on the structure of the given circuit, i.e., numbers of the nodes and sources, and the number of moments to preserve for PRIMA. PRIMA has higher accuracy in general, while the error of R2Power is also in the acceptable range. On the other hand, PRIMA has the higher efficiency than R2Power, only when the numbers of nodes and sources are small enough. Otherwise, R2Power clearly outperforms PRIMA in efficiency. In the memory requirement, the memory size of PRIMA increases very quickly as the numbers of nodes, sources, and preserved moments increase.

• International journal of advanced smart convergence
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• v.1 no.2
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• pp.59-63
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• 2012

The mVoIP service is the technology which focuses on the wireless data service as the IP network having the transmission rate of 100 Mbps classes on the high-speed middle of movement through the WiFi, WiBro and 3G mobile radio communication network, and etc. and is developed. Since 2010, the mVoIP (mobile VoIP) service shows the rapid growth due to 4G-LTE service seriously disclosed from July with the Smart phone and 2,011 it begins to be rapidly popularized. In this research, additionally the mVoIP service industry activation plan is presented with the trends of technology development including the chip-set/module/terminal, etc. based upon local and foreign market trend searchlight through the market demand analysis. The mVoIP service downloads App to the mobile apparatus and or can provide the service as the software through the WiFi network. Therefore, the change which is large in the products development aspect is to be have no. Expected to is being provided as the added service in the case of 4G-LTE as a matter of course, the service deployment where it is based on the market principle and demand needs is needed.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.991-992
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• 2006

Multiprocessor system is efficient and high performance architecture to overcome a limitation of single core SoC. In this paper, we propose a multiprocessor SoC (MPSoC) architecture which provides the low complexity and the high performance. The dynamic routing scheme has a serious problem in which the complexity of routing increases exponentially. We solve this problem by making a cluster with several PEs (Processing Element). In inter-cluster network, we use deterministic routing scheme and in intra-cluster network, we use dynamic routing scheme. In order to control the hierarchical network, we propose efficient router architecture by using smart crossbar switch. We modeled 2-D mesh topology and used simulator based on C/C++. The results of this routing scheme show that our approach has less complexity and improved throughput as compared with the pure deterministic routing architecture and the pure dynamic routing architecture.