• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.12
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• pp.804-810
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• 2004

There are two important things for the general purpose neural network processor. The first is a capability to build various structures of neural network, and the second is to be able to support suitable learning method for that neural network. Some way to process various learning algorithms is required for on-chip learning, because the more neural network types are to be handled, the more learning methods need to be built into. In this paper, an improved hardware structure is proposed to compute various kinds of learning algorithms flexibly. The hardware structure is based on the existing modular neural network structure. It doesn't need to add a new circuit or a new program for the learning process. It is shown that rearrangements of the existing processing elements can produce several neural network learning modules. The performance and utilization of this module are analyzed by comparing with other neural network chips.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1211-1217
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• 2005

Current generation embedded systems are built around only a small number of SOCs, which are again based on general-purpose embedded micro-processors, such as ARM and MIPS. These RISC-based processors are not, however, designed for specific functions such as networking and multimedia processing, whose importances have increased dramatically in recent years. Network devices for small business and home networks, are especially dependent upon such SOCs based on general processors. Except for PHY and MAC layer functions, which are built with hardware, all the network functions are processed by the embedded micro-processor. Enabling technologies such as VDSL and FTTH promise Internet access with a much higher speed, while at the same time explore the limitations of general purpose microprocessors. In this paper we design a network processor, embed it into an SOC for Home gateway, evaluate the performance rigorously, and gauge a possibility for commercialization.

• Journal of computational fluids engineering
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• v.8 no.4
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• pp.41-49
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• 2003

This study presents a numerical model to analyze dynamic thermal behavior of a hot chuck designed for flip-chip bonders. The hot chuck of concern is a heater which has been specifically developed for accomplishing high-speed and ultra-precision soldering. The characteristic features are radiative heat source and the heating tool made of a material of high thermal diffusivity. A physical modeling has been conducted for the network of heat transport. A simplified finite volume model is deviced to simulate time-dependent thermal behavior of the heating tool on which soldering is achieved. The reliability of the proposed numerical model is verified experimentally. A series of numerical tests illustrate the usefulness of the numerical model in design analysis.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.703-706
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• 2004

공정기술의 발달과 컴퓨터 구조적인 발전에 의해서, 시스템의 동작속도가 기하급수적으로 증가하고 있다. 동작속도의 증가는 CMOS로 구현된 chip의 RC 특성에 의해서 timing variation 문제가 발생할 가능성이 높아지면서 테스트 비용이 전체 설계비용에서 차지하게 되는 비중이 급격하게 증가하고 있다. 따라서 온라인 테스트와 진화하드웨어 등이 테스트 비용감소를 위해서 연구되고 있다. 본 논문에서는 네트워크프로세서의 생존성을 위해서, 패킷엔진의 pipline의 각 stage사이의 clock slack borrowing을 이용해서 timing variation 문제를 자체적으로 해결할 수 있다는 것을 mixed-mode simulation을 통해서 통합 검증하였다. 또한 기존의 off-chip 진화하드웨어에 비해서 on-chip구현을 통해서 진화하드웨어의 성능향상과 메모리에 의해서 발생하는 overhead를 감소시키는 것이 가능함을 확인했다.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.309-312
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• 2001

A primitive gas classification system which can classify limited species of gas was designed and simulated. The 'electronic nose' consists of an array of 4 metal oxide gas sensors with different selectivity patterns, signal collecting unit and a signal pattern recognition and decision Part in PLD(programmable logic device) chip. Sensor array consists of four commercial, tin oxide based, semiconductor type gas sensors. BP(back propagation) neutral networks with MLP(Multilayer Perceptron) structure was designed and implemented on CPLD of fifty thousand gate level chip by VHDL language for processing the input signals from 4 gas sensors and qualification of gases in air. The network contained four input units, one hidden layer with 4 neurons and output with 4 regular neurons. The 'electronic nose' system was successfully classified 4 kinds of industrial gases in computer simulation.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.7
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• pp.594-601
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• 2000

EIA-709.1 Control Network Protocol is the basic protocol of LonWorks systems that is emerg-ing as a fieldbus device. In this paper the protocol is implemented by using VHDL with FPGA and C program on an Intel 8051 processor. The protocol from the physical layer to the network layer of EIA-709.1 is im-plemented in a hardware level,. So it decreases the load of the CPU for implementing the protocol. We verify the commercial feasibility of the hardware through the communication test with Neuron Chip. based on EIA-709.1 protocol which is used in industrial fields. The developed protocol based on FPGA becomes one of IP can be applicable to various industrial field because it is implemented by VHDL.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.6
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• pp.566-573
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• 2004

This paper describes the ubiquitous home network (uHome-net) testbed and LonRF intelligent devices based on LonWorks technology. These devices consist of Neuron Chip, RF transceiver, sensor, and other peripheral components. Using LonRF devices, a home control network can be simplified and most devices can be operated on LonWorks control network. Also, Indoor Positioning System (IPS) that can serve various location based services was implemented in uHome-net. Smart Badge of IPS, that is a special LonRF device, can measure the 3D location of objects in the indoor environment. In the uHome-net testbed, remote control service, cooking help service, wireless remote metering service, baby monitoring service and security ＆ fire prevention service were realized. This research shows the vision of the ubiquitous home network that will be emerged in the near future.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.360-361
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• 2006

This paper describes a wire and wireless network sensor for temperature and humidity measurements. The network sensor comprises PLC(Power Line Communication) and RF transmitter(433MHz) for acquiring an internal (on-board) sensor signal, and measured data is transmitted to a main processing unit. The network sensor module is consist of MEMS sensor, 10-bit A/D converter, pre-amp., gain-amp., ADUC812 one chip processor and PLC/RF transmitting unit. The temperature and humidity sensor is based on MEMS piezoelectric membrane structure and is implemented by using dual function sensor for smart home and smart building.

• Bioinformatics and Biosystems
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• v.2 no.2
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• pp.71-74
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• 2007

Cell phenotypes are determined by groups of functionally related genes. Microarray profiling of gene expression provides us response of cellular state to its perturbation. Several methods for uncovering a cellular network show reliable network reconstruction. In this study, we present reconstruction of genetic regulatory network of inflammation bowel disease in human peripheral blood mononuclear cell. The microarray based on Affymetrix Gene Chip Human Genome U133 Array Set HG-U133A is processed and applied network reconstruction algorithm, ARACNe. As a result, we will show that inferred network composed of 450 nodes and 2017 edges is roughly scale-free network and hierarchical organization. The major hub, CCNL2 (cyclin A2), in inferred network is shown to be associated with inflammatory function as well as apoptotic function.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2755-2757
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• 2002

In this paper, we propose a now architecture for hardware implementation of digital neural network. By adopting flexible ladder-style bus and internal connection network into traditional SIMD-type digital neural network architecture, the proposed architecture enables fast processing that is based on parallelism, while does not abandon the flexibility and extensibility of the traditional approach. In the proposed architecture, users can change the network topology by setting configuration registers. Such reconfigurability on hardware allows enough usability like software simulation. We implement the proposed design on real FPGA, and configure the chip to multi-layer perceptron with back propagation for alphabet recognition problem. Performance comparison with its software counterpart shows its value in the aspect of performance and flexibility.