• Proceedings of the Korean Information Science Society Conference
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• 2003.04d
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• pp.286-288
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• 2003

본 논문에서는 서로 다른 네트워크간의 다양한 프로토콜과 이종의 트래픽을 동시에 처리할 수 있는 네트워크용 SoC (System-on-a-Chip) 프로세서를 구현하였다. 제작된 네트워크 SoC 프로세서는 ARM 프로세서 코어와 ATM(Asynchronous Transfer Mode) 블록, 10/100 Mbps 이더넷 볼록, 스케쥴러, UART 등을 이용하였고 각 블록은 AM8A (Advanced Microcontroller Bus Architecture) 버스로 연결하였다. SoC 프로세서는 CADENCE사의 VerilogHDL을 이용하여 설계하였고 0.35$\mu\textrm{m}$ 셀 라이브러리를 이용하여 검증하였다. 구현된 칩은 총 게이트수가 312,000개이며 칠의 최대 동작 주파수는 50MHz 이다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.736-744
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• 2016

Network on chip (NoC) is an emerging technology in the field of multi core interconnection architecture. The routers plays an essential components of Network on chip and responsible for packet delivery by selecting shortest path between source and destination. State-of-the-art NoC designs used routing table to find the shortest path and supports four ports for packet transfer, which consume high power consumption and degrades the system performance. In this paper, the multi port multi core router architecture is proposed to reduce the power consumption and increasing the throughput of the system. The shared buffer is employed between the multi ports of the router architecture. The performance of the proposed router is analyzed in terms of power and current consumption with conventional methods. The proposed system uses Modelsim software for simulation purposes and Xilinx Project Navigator for synthesis purposes. The proposed architecture consumes 31 mW on CPLD XC2C64A processor.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.7
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• pp.647-655
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• 2003

Commonly used SAW duplexers have a difficulty on manufacture so that a transmission line is printed on the package or an LTCC multi-layer is needed because a quarter-wave transmission line which is a kind of an isolation network is applied to the SAW duplexers. In this study, new structures of one chip type SAW duplexers are proposed. In the proposed structure, Tx and Rx SAW ladder filters and isolation networks are located on a single 36LiTaO$_3$ piezoelectric substrate. The manufacture process is very simple than commonly used product. It is possible to improve tile performance by means of optimizing the micro-strip line lumped elements. It is easy to integrate and modulate with other surrounding components. The optimal design techniques can be applied to other kind of multi-port devices.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.75-79
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• 2013

A power distribution network (PDN) is a network that provides connection between the voltage source supply and the power/ground terminals of a microprocessor chip. It consists of a voltage regulator module, a printed circuit board, a package substrate, a microprocessor chip as well as decoupling capacitors. For power integrity analysis, the board and package layouts have to be transformed into an electrical network of resistor, inductor and capacitor components which may be expressed using the S-parameters models. This modeling process generally takes from several hours up to a few days for a complete board or package layout. When the board and package layouts change, they need to be re-extracted and the S-parameters models also need to be re-generated for power integrity assessment. This not only consumes a lot of resources such as time and manpower, the task of PDN modeling is also tedious and mundane. In this paper, a block-based PDN modeling is proposed. Here, the board or package layout is partitioned into sub-blocks and each of them is modeled independently. In the event of a change in power rails routing, only the affected sub-blocks will be reextracted and re-modeled. Simulation results show that the proposed block-based PDN modeling not only can save at least 75% of processing time but it can, at the same time, keep the modeling accuracy on par with the traditional PDN modeling methodology.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.69-74
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• 2013

In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network (PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supply noise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/O interfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individual I/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order to have the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impact on jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise, the on-die noise measurements were measured and results were compared with the original PDN where each I/O and Core PDN are standalone and isolated are used as a benchmark.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.04a
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• pp.7-10
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• 2009

본 연구에서는 차량 네트워크를 구성하는 CAN(Controller Area Network), MOST(Media Oriented System Transport)등의 버스 시스템을 중심으로 IVN(In-Vechicle Network)에 대한 선행연구와 지능형 통합 Gateway 개발 연구를 통해 통합적인 차량 상태정보 수집 및 교환을 위한 차량 Gateway를 제시하고, Soc(System on Chip)형태의 차량용 인터페이스(HMI, Human Machine Interface)를 통한 지능형 통합 GateWay 통신 기술을 OSGi의 번들 형태로 제작하여 알아본다.

• Journal of electromagnetic engineering and science
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• v.11 no.3
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• pp.192-200
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• 2011

This paper proposes a new modeling method for estimating the impedance of an on-chip power/ground meshed plane. Frequency dependent R, L, and C parameters are extracted based on the proposed method so that the model can be applied from DC to high frequencies. The meshed plane model is composed of two parts: coplanar multi strip (CMS) and conductor-backed CMS. The conformal mapping technique and the scaled conductivity concept are used for accurate modeling of the CMS. The developed microstrip approach is applied to model the conductor-backed CMS. The proposed modeling method has been successfully verified by comparing the impedance of RLC circuit based on extracted parameters and the simulated impedance using a 3D-field solver.

• Journal of Internet Computing and Services
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• v.25 no.3
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• pp.1-8
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• 2024

As the Internet of Things (IoT) has gained significant prominence in our daily lives, most IoT devices rely on over-the-air technology to automatically update firmware or software remotely via the network connection to relieve the burden of manual updates by users. And preserving security for OTA interface is one of the main requirements to defend against potential threats. This paper presents a simulation of an attack scenario on the commoditized System-on-a-chip, ESP32 chip, utilized for drones during their OTA update process. We demonstrate three types of attacks, WiFi cracking, ARP spoofing, and TCP SYN flooding techniques and postpone the OTA update procedure on an ESP32 Drone. As in this scenario, unpatched IoT devices can be vulnerable to a variety of potential threats. Additionally, we review the chip to obtain traces of attacks from a forensics perspective and acquire memory forensic artifacts to indicate the SYN flooding attack.

• Journal of Korea Multimedia Society
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• v.12 no.5
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• pp.617-632
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• 2009

In this paper we propose a technique of implementing the reconfigurable network protocol stack that allows for partitioning network protocol functions into software and hardware tasks on a SoC (System on Chip) platform. Additionally, we present a method that guarantees the deadline of both an individual task and messages exchanging among tasks in order to meet the deadline of real-time multimedia and networking services. The proposed real-time message exchange method guarantees the deadline of messages generated by multimedia services that are required to meet the real-time properties of multimedia applications. After implementing the networking functions of TCP/IP protocol suite into hardware and software tasks, we verify and validate their performance on the SoC platform. Experimental results indicate that the proposed technique improves the performance of TCP/IP protocol suit as well as application service satisfaction in application-specific real-time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.8B
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• pp.812-821
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• 2009

This paper proposes a novel dynamically reconfigurable switch for various multimedia applications in hybrid NoC systems. Current NoC systems, which adopt hybrid NoC structure with fixed switch and job distribution algorithms, require designers to precisely predict the property of applications to be processed. This paper proposes a reconfigurable switch which minimizes buffer overflow in various multimedia applications running on an NoC system. To verify the performance of the proposed system, we performed experiments on various multimedia applications running on embedded systems, such as MPEG4 and MP3 decoder, GPS positioning system, and OFDM demodulator. Experimental results show that buffer overflow has been decreased by 41.8% and 29.0%, respectively, when compared with NoC systems having sub-clusters with mesh or star topology. Power usage has been increased by 2.3% compared with hybrid NoC systems using fixed switches, and chip area has been increased from -0.6% to 5.7% depending on sub-cluster topology.