• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.472-474
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• 2002

최근 동영상, 음성 등 멀티미디어 트래픽의 급속한 증가로 네트웍에서 요구되는 전송률은 점점 증가될 전망이다. 이에 따라 라우터도 요구되는 전송률에 대처해 나가기 위해 고속화 되어가고 있다. 이러한 고속 라우터 개발을 가능하게 하는 여러가지 Route Lookup 알고리즘들이 연구되어 왔다. 본 논문에서는 효율적인 Lookup 알고리즘의 원리와 여러 가지 Lookup 알고리즘들에 대해서 알아보고 IXP1200 Network Processor를 이용한 포워딩 엔진 개발에 있어서 사용된 Route Lookup알고리즘을 분석하여 그 효율성에 대해서 연구해 본다.

• Journal of Electrical Engineering and information Science
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• v.3 no.3
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• pp.342-347
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• 1998

An OptiNeural system is developed for optical pattern classification. It is a novel hybrid system which consists of an optical processor and a multilayer neural network. It takes advantages of two dimensional processing capability of an optical processor and nonlinear mapping capability of a neural network. The optical processor with a binary phase only filter is used as a preprocessor for feature extraction and the neural network is used as a decision system through mapping. OptiNeural system is trained for optical pattern classification by use of a simulated annealing algorithm. Its classification performance for grey tone texture patterns is excellent, while a conventional optical system shows poor classification performance.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.1209-1212
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• 2005

By using x86 processor for office environment, an improved Network Display System is implemented in this paper. The Network Display System is developed based on the x86 processor, and the system contains ethernet controller that can be used internet by stand alone. The Windows CE.NET is adopted as an operating system, and TFT-LCD monitor system is embedded..

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.913-914
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• 2006

This paper proposes a flexible IED platform which is implemented with a network processor and a DSP. DSP algorithms are downloaded through the embedded Linux based network processor remotely from ethernet. This architecture gives the best flexibility to adaptively accommodate the various algorithms needed in the IED environment. The developed IED platform can simultaneously measure data of the maximum of forty channels. The developed IED platform shows the successful operation, which measures and transfers the 8 channels data of 16bit samples sampled at 3.84kHz per each channel. The detailed performance analysis of the developed IED platform shows the about 10% processing load of CPU running at 533MHz.

• The Journal of Information Systems
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• v.14 no.3
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• pp.97-104
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• 2005

The paper proposes an implementation architecture of DiffServ-over-MPLS traffic engineering (TE) on Intel IXP2400 network processor using Intel IXA SDK 4.0 Framework. Program architecture and functions are described. Also fast and scalable range-match classification scheme is proposed for DiffServ-over-MPLS TE that has been integrated with functional blocks from Intel Microblocks library. Performance test shows that application can process packets at approximate data rate of 3.5 Gbps. The proposed implementation architecture of DiffServ-over-MPLS TE on Network processor can provide guaranteed QoS on high-speed next generation Internet, while being flexible and easily modifiable.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.34 no.6
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• pp.230-237
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• 1985

Shortest path calculations for a large-scale network have to be performed using a decomposition techniqre, since the calculations require large memory size which increases by the square of the number of vertices in the network. Also, the calculation time increases by the cube of the number of vertices in the network. In the decomposition technique,the network is broken into a number of smaller size subnetworks for each of which shortest paths are computed. A union of the solutions provides the solution of the original network. In all of the decomposition algirithms developed up to now, boundary vertices which divide all the subnetworks have to be included in computing shortest paths for each subnetwork. In this paper, an improved algorithm is developed to reduce the number of boundary vertices to be engaged. In the algorithm, only those boundary vertices that are directly connected to the subnetwork are engaged. The algorithm is suitable for an application to real time computation using a parallel processor system which consists of a number of micro-computers or prcessors. The algorithm has been applied to a 39- vertex network and a 232-vertex network. The results show that it is efficient and has better performance than any other algorithms. A parallel processor system has been built employing an MZ-80 micro-computer and two Z-80 microprocessor kits. The former is used as a master processor and the latter as slave processors. The algorithm is embedded into the system and proven effective for real-time shortest path computations.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.451-453
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• 2007

This paper describes the design of an asynchronous implementation of a sensor network processor. The main purpose of this work is the reduction of power consumption in sensor network node processors and the research presented here tries to explore the suitability of asynchronous circuits for this purpose. The Handshake Solutions toolkit is used to implement an asynchronous version of a sensor processor. The design is made compact, trading area and leakage power savings with dynamic power costs, targeting the typical sparse operating characteristics of sensor node processors. It is then compared with a synchronous version of the same processor. Both versions are then compared with existing commercial processors in terms of power consumption.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.74-81
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• 1997

Xcent-Net is a new system network designed to support a clustered SMP called SPAX(Scalable Parallel Architecture based on Xbar) that is being developed by ETRI. It is a duplicated hierarchical crossbar network to provide the connections among 16 clusters of 128 nodes. Xcent-Net is designed as a packet switched, virtual cut-through routed, point-to-point network. Variable length packets contain up to 64 bytes of data. The packets are transmitted via full duplexed, 32-bit wide channels using source synchronous transmission technique. Its plesiochronous clocking scheme eliminates the global clock distribution problem. Two level priority-based round-robin scheme is adopted to resolve the traffic congestion. Clear-to-send mechanism is used as a packet level flow control scheme. Most of functions are built in Xcent router, which is implemented as an ASIC. This paper describes the architecture and the functional features of Xcent-Net and discusses its implementation.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.6
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• pp.440-445
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• 2004

The design and implementation of a Network Processor using System-on-a-chip(SoC) technology is presented. The proposed network processor can handle several protocols as well as various types of traffics simultaneously. The proposed SoC consists of ARM processor core, ATM block, AAL processing block, Ethernet block and a scheduler. The scheduler guarantees QoS of the voice traffic and supports multiple AAL2 packet. The SoC is manufactured on the 0.35 micron fabrication line of HYNIX semiconductor, the total number of gates is about 312,000, for a maximum operating frequency of over to 50㎒.

• Annual Conference of KIPS
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• 2012.11a
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• pp.42-45
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• 2012

A network processor (NP) is an application-specific instruction-set processor for fast and efficient packet processing. There are many issues in compiler's code generation and optimization due to NP's hardware constraints and special hardware support. In this paper, we describe in detail how to resolve the issues. Our compiler was developed on LLVM 3.0 and the NP target was our in-house network processor which consists of 32 64-bit RISC processors and supports multi-context with special hardware structures. Our compiler incurs only 9.36% code size overhead over hand-written code while satisfying QoS, and the generated code was tested on a real packet processing hardware, called S20 for code verification and performance evaluation.