• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.3
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• pp.245-248
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• 2020

The wettability of silicon carbide (SiC) crystal, which has 6H-SiC and 4H-SiC regions prepared using the physical vapor transport (PVT) method, is quantitatively analyzed using dispensed deionized (DI) water droplets. Regardless of the polytypes in SiC, the average of five contact angle measurements showed a difference of about 6° between the Si-face and C-face. The contact angle on the Si-face (C-face) is measured after the removal of the native oxide using BOE (6:1), and revealed a significant decrease of the contact angle from 74.9° (68.4°) to 47.7° (49.3°) and from 75.8° (70.2°) to 51.6° (49.5°) for the 4H-SiC and 6H-SiC regions, respectively. The contact angle of the Si-face recovered over time during room temperature oxidation in air; in contrast, that of the C-face did not recover to the initial value. This study shows that the contact angle is very sensitive to SiC surface polarity, specific surface conditions, and process time. Contact angle measurements are expected to be a rapid way of determining the surface polarity and wettability of SiC crystals.

• Proceedings of the KIEE Conference
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• 1994.07b
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• pp.1463-1465
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• 1994

The electrical characteristics of $Al/Ta_2O_5/Si$ metal-oxide-semiconductor (MOS) capacitors were studied. $Ta_2O_5$ films on p-type silicon had been prepared by ionized cluster beam epitaxy technique (ICBE). This $Ta_2O_5$ films have low leakage current, high breakdown strength and low flat band shift. In this research, a single crystalline cpitaxial film of $Ta_2O_5$ has been grown on p-Si wafer using an ICBE technique. The native oxide layer ($SiO_2$) on the silicon substrate was removed below $500^{\circ}C$ by use of an accelerated arsenic ion beam, instead of a high temperature deposition. $Ta_2O_5$ films formed by ICBE technique can be received considerable attention for applications to coupling capacitors, gate dielectrics in MOS devices, and memory storage capacitor insulator because of their high dielectric constants above 20 and low temperature process.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.832-834
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• 1992

Using the PECVD method, the silicon nitride films were deposited by changing the $SiH_4/NH_3$ gas flow ratio from 0.2 to 1.4 at an interval of 0.2, AES, FTIR, and Spectroscopic Ellipsomter were used to analyze the film composition and structure, the refractive index, and the deposition rate. Also the C-V analysis was used to estimate the memory performance in the capacitor type MNOS memory devices, which utilized native oxide as the tunneling barrier, with the silicon nitride by the above deposition conditions. As a result, it was confirmed that the performance of MNOS memory devices with PECVD silicon nitride was comparable to that with LPCVD or APCVD silion nitride.

• Transactions of Materials Processing
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• v.13 no.4
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• pp.326-333
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• 2004

The nanoprobe based on lithography, mainly represented by SPM based technologies, has been recognized as a potential application to fabricate the surface nanosctructures because of its operational versatility and simplicity. However, nanoprobe based on lithography itself is not suitable for mass production because it is time a consuming method and not economical for commercial applications. One solution is to fabricate a mold that will be used for mass production processes such as nanoimprint, PDMS casting, and others. The objective of this study is to fabricate the silicon stamper for PDMS casting process by a mastless fabrication technique using the combination of nano/micro machining by Nanoindenter XP and KOH wet etching. Effect of the Berkovich tip alignment on the deformation was investigated. Grooves were machined on a silicon surface, which has native oxide on it, by constant load scratch (CLS), and they were etched in KOH solutions to investigate chemical characteristics of the machined silicon surface. After the etching process, the convex structures was made because of the etch mask effect of the mechanically affected layer generated by nanoscratch. On the basis of this fact, some line patterns with convex structures were fabricated. Achieved groove and convex structures were used as a stamper for PDMS casting process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.10
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• pp.615-624
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• 2017

This study investigated the various physical and electrical effects of silicon direct bonding. Direct bonding means the joining of two wafers together without an intermediate layer. If the surfaces are flat, and made clean and smooth using HF treatment to remove the native oxide layer, they can stick together when brought into contact and form a weak bond depending on the physical forces at room temperature. An IR camera and acoustic systems were used to analyze the voids and bonding conditions in an interface layer during bonding experiments. The I-V and C-V characteristics are also reported herein. The capacitance values for a range of frequencies were measured using a LCR meter. Direct wafer bonding of silicon is a simple method to fuse two wafers together; however, it is difficult to achieve perfect bonding of the two wafers. The direct bonding technology can be used for MEMS and other applications in three-dimensional integrated circuits and special devices.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.20 no.6
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• pp.254-261
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• 2010

Polycrystalline silicon (pc-Si) films are fabricated and characterized for application to pc-Si thin film solar cells as a seed layer. The amorphous silicon films are crystallized by the aluminum-induced layer exchange (ALILE) process with a structure of glass/Al/$Al_2O_3$/a-Si using various thicknesses of $Al_2O_3$ layers. In order to investigate the effects of the oxide layer on the crystallization of the amorphous silicon films, such as the crystalline film detects and the crystal grain size, the $Al_2O_3$ layer thickness arc varied from native oxide to 50 nm. As the results, the defects of the poly crystalline films are increased with the increase of $Al_2O_3$ layer thickness, whereas the grain size and crystallinity are decreased. In this experiments, obtained the average pc-Si sub-grain size was about $10\;{\mu}m$ at relatively thin $Al_2O_3$ layer thickness (${\leq}$ 16 nm). The preferential orientation of pc-Si sub-grain was <111>.

• Transactions of Materials Processing
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• v.12 no.7
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• pp.640-646
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• 2003

The nanoprobe based on lithography, mainly represented by SPM based technologies, has been recognized as potential application to fabricate the surface nanostructures because of its operational versatility and simplicity. The objective of the work is to suggest new mastless pattern fabrication technique using the combination of machining by nanoindenter and KOH wet etching. The scratch option of the nanoindenter is a very promising method for obtaining nanometer scale features on a large size specimen because it has a very wide working area and load range. Sample line patterns were machined on a silicon surface, which has a native oxide on it, by constant load scratch (CLS) of the Nanoindenter with a Berkovich diamond tip, and they were etched in KOH solutions to investigate chemical characteristics of the machined silicon surface. After the etching process, the convex structure was made because of masking effect of the affected layer generated by nano-scratch. On the basis of this fact, some line patterns with convex structures were fabricated. Achieved patterns can be used as a mold that will be used for mass production processes such as nanoimprint or PDMS molding process. All morphological data of scratch traces were scanned using atomic force microscope (AFM).

• Journal of the Korean Ceramic Society
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• v.38 no.8
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• pp.740-748
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• 2001

출발원료 Si 분말의 입자크기를 다양하게 하여 질화반응 및 가스압 소결시 입자크기에 따른 산소함량의 차이에서 나타나는 상변화와 그로 인한 치밀화 거동, 미세구조 발달 및 기계적 특성에 대하여 고찰하였다. 145$0^{\circ}C$의 질화반응에서는 조대분말을 사용한 경우가 미세분말을 사용한 경우보다 높은 질화율을 나타냈으며, 각 분말크기에 따른 native oxide의 함량차에 따라 각기 다른 2차 결정상들이 검출되었다. 조대분말을 사용한 경우에는 제 2상의 석출로 인한 액상량의 부족으로 고온의 소결온도에서도 치밀화를 이루지 못해 낮은 강도값을 나타내었다. 한편, 미세분말을 사용한 경우에는 질화반응 후 석출된 제 2상이 소결온도가 증가함에 따라 용융되면서 치밀화를 이루어 높은 강도값을 나타내었다. 높은 강도값은 미세분말을 사용한 시편들에서 얻어졌으나 높은 파괴인성값은 상대적으로 큰 분말을 사용한 시편들에서 얻어졌는데, 이는 미세한 입자들로 구성된 기지상 내에 잘 발달된 주상정 입자들을 갖는 미세구조에 기인된 것으로 사료된다.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2002.05a
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• pp.40-44
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• 2002

The motivation of this work is to use SAM(Self-Assembled Monolayer) for developing a rapid and flexible non-photolithographic nano-structure fabrication technique which can be utilized in micro-machining of metals as well as silicon-based materials. The fabrication technique implemented in this work consists of a two-step process, namely, mechanical scribing followed by chemical etching. From the experimental results, it was found that thiol on copper surface could be removed even under a few nN normal load. The nano-tribological characteristics of thiol-SAM on various metals were largely dependent on the native oxide layer of metals. Based on these findings, nano-patterns with sub-micrometer width and depth on metal surfaces such as Cu, Au and Ag could be obtained using a diamond-coated tip.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.11
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• pp.887-893
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• 1991

To take advantage of Ti-polycide, when it is contacted with both n+ and p+ active area of silicon, the effects of BF$_2$ on the formation of Ti-silicide were investigated with RTA temperature and dopant concentration. The intermediate phase C49 TiSi$_2$ appeared at $650^{\circ}C$ and the stable phase C54 TiSi2 was formed at $700^{\circ}C$. And the formation of Ti-silicide was hindered by BF$_2$ doping and this trend was decreased with increasing temperature. The out-diffusion phenomena of BF$_2$ into Ti silicide were not observed. And significantly, the native oxide was a chief factor preventing the formation of Ti-silicides.