• Transactions on Electrical and Electronic Materials
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• 제11권3호
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• pp.93-105
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• 2010

Complementary metal-oxide-semiconductor (CMOS) technology scaling has been a main key for continuous progress in silicon-based semiconductor industry over the past three decades. However, as the technology scaling enters nanometer regime, CMOS devices are facing many serious problems such as increased leakage currents, difficulty on increase of on-current, large parameter variations, low reliability and yield, increase in manufacturing cost, and etc. To sustain the historical improvements, various innovations in CMOS materials and device structures have been researched and introduced. In parallel with those researches, various new nanoelectronic devices, so called "Beyond CMOS Devices," are actively being investigated and researched to supplement or possibly replace ultimately scaled conventional CMOS devices. While those nanoelectronic devices offer ultra-high density system integration, they are still in a premature stage having many critical issues such as high variations and deteriorated reliability. The practical realization of those promising technologies requires extensive researches from device to system architecture level. In this paper, the current researches and challenges on nanoelectronics are reviewed and critical tasks are summarized from device level to circuit design/CAD domain to better prepare for the forthcoming technologies.

• 센서학회지
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• 제16권4호
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• pp.313-318
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• 2007

Single-wall carbon nanotube field-effect transistors (SWCNT FETs) of top gate structure were fabricated in a conventional metal-oxide-semiconductor field effect transistor (MOSFET) with gate electrodes above the conduction channel separated from the channel by a thin $SiO_{2}$ layer. The carbon nanotubes (CNTs) directly grown using thin Fe film as catalyst by thermal chemical vapor deposition (CVD). These top gate devices exhibit good electrical characteristics, including steep subthreshold slope and high conductance at low gate voltages. Our experiments show that CNTFETs may be competitive with Si MOSFET for future nanoelectronic applications.

• 한국전기전자재료학회논문지
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• 제29권9호
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• pp.571-575
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• 2016

Recently, there has been much focus on the controlled alignment and patterning process of nanowires for nanoelectronic devices. A simple and effective method for patterning of highly aligned nanowires using a microcontact printing technique is demonstrated. In this method, nanowires are first directionally aligned by contact printing, following which line and space micropatterns of nanowire arrays are accomplished by microcontact printing with a micro patterned NOA mold.

• Applied Microscopy
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• 제46권4호
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• pp.206-216
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• 2016

This communication is to elucidate the state-of-the-art of techniques necessary to gather information on a new class of nanoelectronic devices known as memristors and related resistive switching devices, respectively. Unlike classical microelectronic devices such as transistors, the chemical and structural variations occurring upon switching of memristive devices require cutting-edge electron microscopy techniques. Depending on the switching mechanism, some memristors call for the acquisition of atomically resolved structural data, while others rely on atomistic chemical phenomena requiring the application of advanced X-ray and electron spectroscopy to correlate the real structure with properties. Additionally, understanding resistive switching phenomena also necessitates the application not only of pre- and post-operation analysis, but also during the process of switching. This highly challenging in situ characterization also requires the aforementioned techniques while simultaneously applying an electrical bias. Through this review we aim to give an overview of the possibilities and challenges as well as an outlook onto future developments in the field of nanoscopic characterization of memristive devices.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.575-575
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• 2012

Synthesis of novel two dimensional materials has gained tremendous attention recently as they are considered as alternative materials for replacing graphene that suffers from a lack of bandgap, a property that is essential for many applications. Single layer molybdenum disulfide ($MoS_2$) has a direct bandgap (1.8eV) that is promising for use in next-generation optoelectronics and energy harvesting devices. We have successfully grown high quality single layer $MoS_2$ by a facile vapor-solid transport route. As-grown single layer $MoS_2$ was carefully characterized by using X-ray diffraction, Raman spectroscopy, field emission scanning electron microscopy and electrical transport measurement. The results indicate that a high quality single layer $MoS_2$ can be successfully grown on silicon substrate. This may open up great opportunities for the exploration of novel nanoelectronic devices.

• Advances in nano research
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• 제5권1호
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• pp.61-67
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• 2017

A semi-empirical approach to model the temperature effects on I-V characteristics of Carbon Nanotube Field Effect Transistors (CNTFETs) is proposed. The model includes two thermal parameters describing CNTFET behaviour in terms of saturation drain current and threshold voltage, whose values are extracted from the simulated and trans-characteristics of the device in different temperature conditions. Our results are compared with those of a numerical model online available, obtaining I-V characteristics comparable but with a lower CPU calculation time.

• 전자통신동향분석
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• 제20권5호통권95호
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• pp.28-45
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• 2005

무어의 법칙을 근간으로 하는 전계효과 트랜지스터는 매 18개월마다 0.7배씩의 성공적인 소형화를 거듭하여 최근에는 50nm 크기로 구성된 약 1억 개의 트랜지스터가 집적된 칩을 생산하고 있다. 그러나 트랜지스터의 크기가 50nm 이하로 줄어들면서는 단순한 소형화 과정은 근본적인 물리적인 한계에 접근하게 되었다. 특히 게이트 절연막의최소 두께는 트랜지스터의 소형화에 가장 직접적인 중요한 요소이나, 실리콘 산화막의 두께가 2nm 이하가 되면서 게이트 절연막을 집적 터널링하는 전자에 의한 누설전류의 급격한 증가로 인하여 그 사용이 어려워지고 있는 추세이다. 따라서 본 논문에서는 트랜지스터의 소형화에 악영향을 미치는 물리적인 한계요소에 대하여 살펴보고, 이러한 소형화의 한계를 뛰어넘기 위한 노력의 일환으로 연구되고 있는 이중게이트 구조의 트랜지스터, 쇼트키 트랜지스터, 나노선을 이용한 트랜지스터 및 분자소자 등의 새로운 소자구도에 대하여 살펴보고자 한다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.1049-1052
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• 2007

Extremely sharp and uniform Transfer Mold FEAs with thin film low work function TiN emitter material have been fabricated by controlling the thickness of the coated emitter materials to realize high efficient, high reliable and low-cost vacuum nanoelectronic devices..Their tip radii are 8.3-13.8 nm. Turn-on electric fields of the Ni FEAs and TiN-FEAs resulted in the low electric field values of $31.6\;V/{\mu}m$ and $44.2V/{\mu}m$,respectively, at the short emitter/anode distance: less than $30\;{\mu}m$, which are lower than those of conventional FE As such as Spindt type FEAs and carbon nan otube FEAs The Transfer Metal Mold fabrication method is one of the best methods of changing emit ter materials with sharp and uniform emit ter shapes.

• Advances in nano research
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• 제9권2호
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• pp.105-112
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• 2020

Silicene is a two-dimensional (2D) derivative of silicon (Si) arranged in honeycomb lattice. It is predicted to be compatible with the present fabrication technology. However, its gapless properties (neglecting the spin-orbiting effect) hinders its application as digital switching devices. Thus, a suitable band gap engineering technique is required. In the present work, the band structure and density of states of uniformly doped silicene are obtained using the nearest neighbour tight-binding (NNTB) model. The results show that uniform substitutional doping using aluminium (Al) has successfully induced band gap in silicene. The band structures of the presented model are in good agreement with published results in terms of the valence band and conduction band. The band gap values extracted from the presented models are 0.39 eV and 0.78 eV for uniformly doped silicene with Al at the doping concentration of 12.5% and 25% respectively. The results show that the engineered band gap values are within the range for electronic switching applications. The conclusions of this study envisage that the uniformly doped silicene with Al can be further explored and applied in the future nanoelectronic devices.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2009년도 춘계학술발표대회
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• pp.24.2-24.2
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• 2009

Nanostuctures such as nanodot and nanowire have been extensively studied as building blocks for nanoscale devices. However, the direct growth of the nanostuctures at the desired position is one of the most important requirements for realization of the practical devices with high integrity. Self-assembled nanotemplate is one of viable methods to produce highly-ordered nanostructures because it exhibits the highly ordered nanometer-sized pattern without resorting to lithography techniques. And selective epitaxial growth (SEG) can be a proper method for nanostructure fabrication because selective growth on the patterned openings obtained from nanotemplate can be a proper direction to achieve high level of control and reproducibility of nanostructucture fabrication. Especially, SiGe has led to the development of semiconductor devices in which the band structure is varied by the composition and strain distribution, and nanostructures of SiGe has represented new class of devices such nanowire metal-oxide-semiconductor field-effect transistors and photovoltaics. So, in this study, various shaped SiGe nanostructures were selectively grown on Si substrate through ultrahigh vacuum chemical vapor deposition (UHV-CVD) of SiGe on the hexagonally arranged Si openings obtained using nanotemplates. We adopted two types of nanotemplates in this study; anodic aluminum oxide (AAO) and diblock copolymer of PS-b-PMMA. Well ordered and various shaped nanostructure of SiGe, nanodots and nanowire, were fabricated on Si openings by combining SEG of SiGe to self-assembled nanotemplates. Nanostructure fabrication method adopted in this study will open up the easy way to produce the integrated nanoelectronic device arrays using the well ordered nano-building blocks obtained from the combination of SEG and self-assembled nanotemplates.