• Journal of the Korean Society for Precision Engineering
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• v.32 no.10
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• pp.911-916
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• 2015

In the nano/micro scale, material properties are dependent on the size-scale of a structure. However, conventional micro-scale tensile tests have limitations to obtain reliable values of nano-scale material properties owing to residual stress and elastic slippage in the gripping/aligning process. The indenter-driven nano-scale tensile test provides prominent advantages simple testing device, high-quality nano-scale metallic specimen with negligible residual stress. In this paper, two-types of specimens (a specimen with multi-testing parts and a specimen with a single-testing part) are discussed. Focused ion beam (FIB) is employed to fabricate a nano-scale specimen from a thin nickel film. Using the specimen with a single-testing part, we obtained a nano-scale stress-strain curve of electroplated nickel film.

• Proceedings of the Korean Magnestics Society Conference
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• 2003.12a
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• pp.85-85
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• 2003

• Journal of Magnetics
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• v.12 no.1
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• pp.12-16
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• 2007

Magnetic excitation and reversal by a spin polarized current via spin transfer have been a central research topic in spintronics due to its application potential. Special techniques are required to fabricate nano-scale magnetic layers in which the effect can be observed and studied. This work discusses the possibility of using electron-beam resists, the nano-scale patterning media, as ion milling mask in a subtractive fabrication method. The possibility is demonstrated by two resists, one positive tone, the ZEP 520A, and one negative tone, the ma-N2403. The advantage and the key points for success of this process will be also addressed.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.10a
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• pp.665-666
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• 2006

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.21-29
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• 2004

Hot carrier degradation characteristics of Nano-scale CMOSFETs with dual gate oxide have been analyzed in depth. It is shown that, PMOSFET lifetime dominate the device lifetime than NMOSFET In Nano-scale CMOSFETs, that is, PMOSFET lifetime under CHC (Channel Hot Carrier) stress is much lower than NMOSFET lifetime under DAHC (Dram Avalanche Hot Carrier) stress. (In case of thin MOSFET, CHC stress showed severe degradation than DAHC for PMOSFET and DAHC than CHC for NMOSFET as well known.) Therefore, the interface trap generation due to enhanced hot hole injection will become a dominant degradation factor in upcoming Nano-scale CMOSFET technology. In case of PMOSFETs, CHC shows enhanced degradation than DAHC regardless of thin and thick PMOSFETs. However, what is important is that hot hole injection rather than hot electron injection play a important role in PMOSFET degradation i.e. threshold voltage increases and saturation drain current decreases due to the hot carrier stresses for both thin and thick PMOSFET. In case of thick MOSFET, the degradation by hot carrier is confirmed using charge pumping current method. Therefore, suppression of PMOSFET hot carrier degradation or hot hole injection is highly necessary to enhance overall device lifetime or circuit lifetime in Nano-scale CMOSFET technology

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.05a
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• pp.529-530
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• 2010

• Advances in biomechanics and applications
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• v.1 no.1
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• pp.23-40
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• 2014

This paper examines the blood chamber of a left ventricular assist device (LVAD) under static loading conditions and standard operating temperatures. The LVAD's walls are made of a temperature-sensitive polymer (ChronoFlex C 55D) and are covered with a titanium nitride (TiN) nano-coating (deposited by laser ablation) to improve their haemocompatibility. A loss of cohesion may be observed near the coating-substrate boundary. Therefore, a micro-scale stress-strain analysis of the multilayered blood chamber was conducted with FE (finite element) code. The multi-scale model included a macro-model of the LVAD's blood chamber and a micro-model of the TiN coating. The theories of non-linear elasticity and elasto-plasticity were applied. The formulated problems were solved with a finite element method. The micro-scale problem was solved for a representative volume element (RVE). This micro-model accounted for the residual stress, a material model of the TiN coating, the stress results under loading pressures, the thickness of the TiN coating and the wave parameters of the TiN surface. The numerical results (displacements and strains) were experimentally validated using digital image correlation (DIC) during static blood pressure deformations. The maximum strain and stress were determined at static pressure steps in a macro-scale FE simulation. The strain and stress were also computed at the same loading conditions in a micro-scale FE simulation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.7
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• pp.569-574
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• 2007

In this paper, the reliability (NBTI degradation: ${\Delta}V_{th}$) and device characteristic of nano-scale PMOSFET with plasma nitrided oxide (PNO) is characterized in depth by comparing those with thermally nitrided oxide (TNO). PNO case shows the reduction of gate leakage current and interface state density compared to TNO with no change of the $I_{D.sat}\;vs.\;I_{OFF}$ characteristics. Gate oxide capacitance (Cox) of PNO is larger than TNO and it increases as the N concentration increases in PNO. PNO also shows the improvement of NBTI characteristics because the nitrogen peak layer is located near the $Poly/SiO_2$ interface. However, if the nitrogen concentration in PNO oxide increases, threshold voltage degradation $({\Delta}V_{th})$ becomes more degraded by NBT stress due to the enhanced generation of the fixed oxide charges.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.18-26
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• 2004

Back-gated silicon-on-insulator MOSFET -a threshold-voltage adjustable device-employs a constant back-gate potential to terminate source-drain electric fields and to provide carrier confinement in the channel. This suppresses shortchannel effects of nano-scale and of high drain biases, while allowing a means to threshold voltage control. We report here a theoretical analysis of this geometry to identify its natural length scales, and correlate the theoretical results with experimental device measurements. We also analyze experimental electrical characteristics for misaligned back-gate geometries to evaluate the influence on transport behavior from the device electrostatics due to the structure and position of the back-gate. The backgate structure also operates as a floating-gate nonvolatile memory (NVRAM) when the back-gate is floating. We summarize experimental and theoretical results that show the nano-scale scaling advantages of this structure over the traditional front floating-gate NVRAM.

• Proceedings of the KWS Conference
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• 2009.11a
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• pp.235-238
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• 2009

To study the relationship between spark ignition and the gap in the nano-scale region, the electric potential was applied to between a Pt-Ir tip and a gold substrate. The tip was sharpened by electro-chemical etching process in the solution of $CaCl_2;H_2O$ and acetone. The radius of tip was measured to be around 200nm and attached to the scanning probe microscope to control the gap between the tip and the substrate. The electric potential of 10V to 80V was applied to initialize the spark. The gaps and the current profile were measured to analyze the characteristics of spark ignition. A spark sustaining time was measured to be between 50ns and 200ns depending on the applied electric potential and the gap between the electrodes. The continuous electric discharge was successfully sustained up to 1 second of spark or arc time. The developed process can be applicable to the micro-scale fabrication of automotive sensors as a similar concept of GTAW.