• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.12
• /
• pp.24-29
• /
• 2009

In order to model the high temperature dependence of the cutoff frequency $f_T$ in $0.18{\mu}m$ deep n-well isolated bulk NMOSFET, high temperature data of electron velocity of bulk MOSFETs from $30^{\circ}C$ to $250^{\circ}C$ are obtained by an accurate RF extraction method using measured S-parameters. From these data, an improved temperature-dependent electron velocity equation is developed and implemented in a BSIM3v3 SPICE model to eliminate modeling error of a conventional one in the high temperature range. Better agreement with measured $f_T$ data from $30^{\circ}C$ to $250^{\circ}C$ are achieved by using the SPICE model with the improved equation rather than the conventional one, verifying its accuracy of the improved one.

• Journal of the Korean Vacuum Society
• /
• v.17 no.3
• /
• pp.199-203
• /
• 2008

The effects of surface treatment by $O_2$ plasma on the Bio-FETs were investigated by using the pseudo-MOSFETs on the SOI substrates. After a surface treatment by $O_2$ plasma with different RF powers, the current-voltage and field effect mobility of pseudo-MOSFETs were measured by applying back gate bias. The subthreshold characteristics of pseudo-MOSFETs were significantly degraded with increase of RF power. Additionally, a forming gas anneal process in 2 % diluted $H_2/N_2$ ambient was developed to recover the plasma process induced surface damages. A considerable improvement of the subthreshold characteristics was achieved by the forming gas anneal. Therefore, it is concluded that the pseudo-MOSFETs are a powerful tool for monitoring the surface treatment of Bio-FETs and the forming gas anneal process is effective for improving the electrical characteristics of Bio-FETs.

• Journal of Sensor Science and Technology
• /
• v.12 no.4
• /
• pp.149-155
• /
• 2003

A PMOSFET photodetector for highly-sensitive active pixel sensor(APS) is presented. This sensor uses 5V power supply and has been designed and fabricated using I-poly and 2-metal $1.5{\mu}m$ CMOS technology. The feature of a PMOSFET photodetector is that the polysilicon gate of the PMOSFET was connected to n-well, in order to increase the photo sensitivity. The designed MOS photodetector has similar $I_{DS}-V_{DS}$ characteristics with a standard MOSFET. One dimensional image sensor with 16 pixels based on the PMOSFET photodetector has also been designed and fabricated. Unit pixel of the designed sensor consists of a PMOSFET photodetector and 4 NMOSFETs. Unit pixel area is $86{\mu}m{\times}90.5{\mu}m$ and its fill factor is about 12%.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.11
• /
• pp.49-54
• /
• 1990

In this paper, a simple model is presented for the gate-voltage dependence of the parasitic resistance in MOSFETs with the lightly-doped drain (LDD) structure. At the LDD region located under the gate electrode, an accumulation layer is formed due to the gate voltage. The parasitic resistance of the source side LDD in the channel is treated as a parallel combination of the resistance of the accumulation layer and that of the bulk LDD, which is approximated as a spreading resistance from the end of the channel inversion layer to the ${n^+}$/LDD junction boundary. Also the effects of doping gradients at the junction are discussed. As result of the model, the LDD resistance decreases with increasing the gate voltage at the linear regime, and increase quasi-linearly with the gate voltage at the saturation regime, considering th velocity saturation both in the channel and in the LDD region. The results are in good agreement with experimental data reported by others.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2014.10a
• /
• pp.749-752
• /
• 2014

The device performance of n-channel MuGFET with different fin width, existence of spacer and channel length has been characterized. Tri-Gate structure(fin number=10) has been used. There are four kinds of Tri-Gate with fin width=55nm with spacer, fin width=70nm with spacer, fin width=55nm without spacer, fin width=70nm without spacer. DIBL, subthreshold swing, Vt roll-off, (above Short Channel Effect)and hot carrier stress degradation have been measured. From the experiment results, short Channel Effect with spacer was decreased, hot carrier degradation with spacer and narrow fin width was decreased. Therefore, layout of LDD structure with spacer and narrow fin width is desirable in short channel effect and hot carrier degradation.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.2
• /
• pp.306-316
• /
• 2016

In this paper, an NMOS-diode eFuse OTP (One-Time Programmable) memory cell is proposed using a parasitic junction diode formed between a PW (P-Well), a body of an isolated NMOS (N-channel MOSFET) transistor with the small channel width, and an n+ diffusion, a source node, in a DNW (Deep N-Well) instead of an NMOS transistor with the big channel width as a program select device. Blowing of the proposed cell is done through the parasitic junction formed in the NMOS transistor in the program mode. Sensing failures of '0' data are removed because of removed contact voltage drop of a diode since a NMOS transistor is used instead of the junction diode in the read mode. In addition, a problem of being blown for a non-blown eFuse from a read current through the corresponding eFuse OTP cell is solved by limiting the read current to less than $100{\mu}A$ since a voltage is transferred to BL by using an NMOS transistor with the small channel width in the read mode.

• Journal of Satellite, Information and Communications
• /
• v.9 no.2
• /
• pp.12-17
• /
• 2014

In this paper, modified EDNMOS device with DPS (double polarity source) structure are suggested to realize stable and robust ESD (electrostatic discharge) protection performance of high voltage operating microchip. This DPS structure inserts the P+ diffusion layer on N+ source side, which in intended to block lateral extension of the electron rich region from N+ source side. Based on our simulation results, the inserted P+ diffusion layer effectively prevents the formation of deep electron channeling induced by high electron injection. As a result, our proposed DPS_EDNMOS devices could overcome the double snapback effect of conventional Std_EDNMOS device.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.2
• /
• pp.210-214
• /
• 2016

In this paper, the decrease in the contact resistance of Ni germanide/Ge contact was studied as a function of the thickness of the antimony (Sb) interlayer for high performance Ge MOSFETs. Sb layers with various thickness of 2, 5, 8 and 12 nm were deposited by RF-Magnetron sputter on n-type Ge on Si wafers, followed by in situ deposition of 15nm-thick Ni film. The contact resistance of samples with the Sb interlayer was lower than that of the reference sample without the Sb interlayer. We found that the Sb interlayer can lower the contact resistance of Ni germanide/Ge contact but the reduction of contact resistance becomes saturated as the Sb interlayer thickness increases. The proposed method is useful for high performance n-channel Ge MOSFETs.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.19 no.10
• /
• pp.894-900
• /
• 2006

This paper reports the fabrication and characterization of $32{\times}32$ thermal cantilever array for nano-scaled memory device applications. The $32{\times}32$ thermal cantilever array with integrated tip heater has been fabricated with micro-electro-mechanical systems(MEMS) technology on silicon on insulator(SOI) wafer using 9 photo masking steps. All of single-level cantilevers(1,024 bits) have a p-n junction diode in order to eliminate any electrical cross-talk between adjacent cantilevers. Nonlinear electrical characteristic of fabricated thermal cantilever shows its own thermal heating mechanism. In addition, n-channel high-voltage MOSFET device is integrated on a wafer for embedding driver circuitry.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2003.03a
• /
• pp.106-106
• /
• 2003

반도체 소자의 고집적화에 따라 채널길이와 배선선 폭은 점차 줄어들고, 이에 따라 단채널효과, 소스/드레인에서의 기생저항 증가 및 게이트에서의 RC 시간지연 증가 등의 문제가 야기되었다. 이를 해결하기 위하여 자기정렬 실리사이드화(SADS) 공정을 통해 TiSi2, CoSi2 같은 금속 실리사이드를 접촉 및 게이트 전극으로 사용하려는 노력이 진행되고 있다. 그런데 TiSi2는 면저항의 선폭의존성 때문에, 그리고 CoSi2는 실리사이드 형성시 과도한 Si소모로 인해 차세대 MOSFET소자에 적용하기에는 한계가 있다. 반면, NiSi는 이러한 문제점을 나타내지 않고 저온 공정이 가능한 재료이다. 그러나, NiSi는 실리사이드 형성시 NiSi/Si 계면의 산화와 거침성(roughness) 때문에 높은 누설 전류와 면저항값, 그리고 열적 불안정성을 나타낸다. 한편, 초고집적 소자의 배선재료로는 비저항이 낮고 electro- 및 stress-migration에 대한 저항성이 높은 Cu가 사용될 전망이다. 그러나, Cu는 Si, SiO2, 실리사이드로 확산·반응하여 소자의 열적, 전기적, 기계적 특성을 저하시킨다. 따라서 Cu를 배선재료로 사용하기 위해서는 확산방지막이 필요하며, 확산방지재료로는 Ti, TiN, Ta, TaN 등이 많이 연구되고 있다.