• Journal of Satellite, Information and Communications
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• v.11 no.4
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• pp.27-32
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• 2016

A conventional double diffused drain n-type MOSFET (DDD_NMOS) device shows SCR behaviors with very low snapback holding voltage and latch-up problem during normal operation. However, a modified DDD_NMOS-based silicon controlled rectifier (DDD_NSCR_CPS) device with a counter pocket source (CPS) structure is proven to increase the snapback holding voltage and on-resistance compare to standard DDD_NSCR device, realizing an excellent electrostatic discharge protection performance and the stable latch-up immunity.

• Journal of Electrical Engineering and information Science
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• v.3 no.2
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• pp.261-266
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• 1998

This paper describes the fabrication and characterization of dual-polysilicon gated surface channel 0.1$\mu\textrm{m}$ CMOSFETs using BF2 and arsenic as channel dopants. We have used and LDD structure and 40${\AA}$ gate oxide as an insulator. To suppress short channel effects down to 0.1$\mu\textrm{m}$ channel length, shallow source/drain extensions implemented by low energy implantation and SSR(Super Steep Retrograde) channel structure were used. The threshold voltages of fabricated CMOSFETs are 0.6V. The maximum transconductance of nMOSFET is 315${\mu}$S/$\mu\textrm{m}$, and that of pMOSFET is 156 ${\mu}$S/$\mu\textrm{m}$. The drain saturation current of 418 ${\mu}$A/$\mu\textrm{m}$, 187${\mu}$A/$\mu\textrm{m}$ are obtained. Subthreshold swing is 85mV/dec and 88mV/dec, respectively. DIBL(Drain Induced Barrier Lowering) is below 100mV. In the device with 2000${\AA}$ thick gate polysilicon, depletion in polysilicon near the gate oxide results in an increase of equivalent gate oxide thickness and degradation of device characteristics. The gate delay time is measured to be 336psec at operation voltage of 2V.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.46-52
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• 2012

Separate extraction of source ($R_S$) and drain ($R_D$) resistances caused by process, layout variations and long term degradation is very important in modeling and characterization of MOSFETs. In this work, we propose "Avalanche Hot-Source Method (AHSM)" for simple separated extraction of $R_S$ and $R_D$ in a single device. In AHSM, the high field region near the drain works as a new source for abundant carriers governing the current-voltage relationship in the MOSFET at high drain bias. We applied AHSM to n-channel MOSFETs as single-finger type with different channel width/length (W/L) combinations and verified its usefulness in the extraction of $R_S$ and $R_D$. We also confirmed that there is a negligible drift in the threshold voltage ($V_T$) and the subthreshold slope (SSW) even after application of the method to devices under practical conditions.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.21-24
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• 2004

Pseudo-MOSFET의 제작을 위해서는 표면 실리콘 층의 식각 공정이 필요하며, 공정의 간편성으로 인해 주로 RIE(Reactive Ion Etching)를 사용하고 있다. 하지만, RE 공정 도중 발생하는 Plasma에 의해서 SOI 층이 손상을 받게 되고 이 영향으로 소자의 특성이 열화 될 가능성이 있다. 이러한 특성의 열화를 확인하기 위하여 소자 제작을 위한 표면 실리콘 층의 식각을 RIE 공정과 TMAH 용액을 이용한 습식 식각을 각각 행하여 그 특성을 비교한 결과, 건식 식각된 시편에서 계면상태 밀도의 증가, 이동도의 감소 등 특성 열화 현상이 현저히 나타났다. 이러한 RIE 공정 중 발생하는 손상을 제거하기 위하여 저온 열처리를 하였으며 그 결과 $400^{\circ}C$ $N_2$ 분위기에서 4시간 동안 열처리를 하여 습식 식각된 시편과 동일한 특성을 가지게 할 수 있었다.

• Transactions on Electrical and Electronic Materials
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• v.12 no.3
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• pp.93-97
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• 2011

In this paper, we discuss design considerations for an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a lateral asymmetric channel (LAC) doping profile. We employed a 0.35 ${\mu}M$ standard complementary MOSFET process for fabrication of the devices. The gates to the LAC doping overlap lengths were 0.5, 1.0, and 1.5 ${\mu}M$. The drain current ($I_{ON}$), transconductance ($g_m$), substrate current ($I_{SUB}$), drain to source leakage current ($I_{OFF}$), and channel-hot-electron (CHE) reliability characteristics were taken into account for optimum device design. The LAC devices with shorter overlap lengths demonstrated improved $I_{ON}$ and $g_m$ characteristics. On the other hand, the LAC devices with longer overlap lengths demonstrated improved CHE degradation and $I_{OFF}$ characteristics.

• ETRI Journal
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• v.35 no.4
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• pp.632-637
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• 2013

In this paper, we propose a superjunction trench gate MOSFET (SJ TGMOSFET) fabricated through a simple p-pillar forming process using deep trench and boron silicate glass doping process technology to reduce the process complexity. Throughout the various boron doping experiments, as well as the process simulations, we optimize the process conditions related with the p-pillar depth, lateral boron doping concentration, and diffusion temperature. Compared with a conventional TGMOSFET, the potential of the SJ TGMOSFET is more uniformly distributed and widely spread in the bulk region of the n-drift layer due to the trenched p-pillar. The measured breakdown voltage of the SJ TGMOSFET is at least 28% more than that of a conventional device.

• Transactions on Electrical and Electronic Materials
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• v.11 no.1
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• pp.24-28
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• 2010

A simulation study of a current-mode direct current (DC)-DC buck converter is presented in this paper. The converter, with a fully integrated power module, is implemented by using sense method metal-oxide-semiconductor field-effect transistor (MOSFET) and bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. When the MOSFET is used in a current sensor, the sensed inductor current with an internal ramp signal can be used for feedback control. In addition, the BiCMOS technology is applied in the converter for an accurate current sensing and a low power consumption. The DC-DC converter is designed using the standard $0.35\;{\mu}m$ CMOS process. An off-chip LC filter is designed with an inductance of 1 mH and a capacitance of 12.5 nF. The simulation results show that the error between the sensing signal and the inductor current can be controlled to be within 3%. The characteristics of the error amplification and output ripple are much improved, as compared to converters using conventional CMOS circuits.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.1
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• pp.88-96
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• 2016

In this paper, the GaN FET based phase-shift full-bridge dc-dc converter design is implemented. Switch characteristics of GaN FET were analyzed in detail by comparing state-of-the-art Si MOSFET. Owing to the low conduction resistance and parasitic capacitance, it is expected to GaN FET based power conversion system has improved performance. However, GaN FET is vulnerable to electric interference due to the relatively low threshold voltage and fast switching transient. Therefore, it is necessary to consider PCB layout to design GaN FET based power system because PCB layout is the main reason of stray inductance. To reduce the electric noise, gate voltage of GaN FET is analyzed according to operation mode of phase-shift full-bridge dc-dc converter. Two 600W phase-shifted full-bridge dc-dc converter are designed based on the result to evaluate effects of stray inductance.

• Journal of Electrical Engineering and Technology
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• v.10 no.3
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• pp.1131-1137
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• 2015

Gallium nitride (GaN) is a promising material for next-generation high-power applications due to its wide bandgap, high breakdown field, high electron mobility, and good thermal conductivity. From a structure point of view, the vertical device is more suitable to high-power applications than planar devices because of its area effectiveness. However, it is challenging to obtain a completely upright vertical structure due to inevitable sidewall slope in anisotropic etching of GaN. In this letter, we design and analyze the enhancement-mode n-channel vertical GaN MOSFET with variation of sidewall gate angle by two-dimensional (2D) technology computer-aided design (TCAD) simulations. As the sidewall slope gets closer to right angle, the device performances are improved since a gradual slope provides a leakage current path through the bulk region.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.4
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• pp.297-304
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• 2017

The purpose of this paper is to analyze losses because of switching devices and the secondary side circuit diodes of 500 W full bridge dc-dc converter by applying gallium nitride (GaN) field-effect transistor (FET), which is one of the wide band gap devices. For the detailed device analysis, we translate the specific resistance relation caused by the GaN FET material property into algebraic expression, and investigate the influence of the GaN FET structure and characteristic on efficiency and system specifications. In addition, we mathematically compare the diode rectifier circuit loss, which is a full bridge dc-dc converter secondary side circuit, with the synchronous rectifier circuit loss using silicon metal-oxide semiconductor (Si MOSFET) or GaN FET, which produce the full bridge dc-dc converter analytical value validity to derive the final efficiency and loss. We also design the heat sink based on the mathematically derived loss value, and suggest the heat sink size by purpose and the heat divergence degree through simulation.