• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.350-350
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• 2013

Sol-gel법을 이용하여 p-Si 기판위에 yttrium이 도핑된 ZnO (YZO)를 성장하였다. ZnO의 precursor로는 zinc acetate dihydrate를, yttrium의 source로는 yttrium acetate hydrate를 사용하였으며, 용매와 안정제로는 각각 2-methoxy ethanol과 monoethanolamine (MEA)를 사용하였다. yttrium의 doping 농도에 따른 영향을 알아보기 위하여 1~4 at.%로 제작된 YZO sol을 각각 p-type Si 기판에 성장하였으며, 이 후 furnace를 이용하여 500oC에서 1시간 동안 열처리하였다. 성장된 YZO 박막의 표면과 두께를 SEM을 통하여 확인하였으며, XRD를 통한 구조적인 특성을 분석한 결과 모든 박막에서 뚜렷한 c-축 배양성을 갖는 ZnO (0002)피크를 확인하였다. Hall effect를 통하여 YZO는 모두 n-type 특성을 나타낸다는 것을 확인하였으며, 광학적인 특성은 PL을 통해서 분석하였다. n-YZO/p-Si 이종접합의 전류-전압 특성을 분석한 결과 뚜렷한 정류특성을 나타내었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.94-94
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• 2008

We have performed simulation for Junction Field Effect Transistor(JFET) using Silvco to improve its electrical properties. The device structure and process conditions of Si-control JFET(Si-JFET) were determined to set its cut off voltage and drain current(at Vg=0V) to -0.5V and $300{\mu}A$, respectively. From electrical property obtained at various implantation energy, dose, and drive-in conditions of p-gate doping, we found that the drive in time of p-type gate was the most determinant factor due to severe diffusion. Therefore we newly designed SiGe-JFET, in which SiGe layer is to epitaxial layers placed above and underneath of the Si-channel. The presence of SiGe layer lessen the p-type dopants (Boron) into the n-type Si channel the phenomenon would be able to enhance the structural consistency of p-n-p junction. The influence of SiGe layer will be discussed in conjunction with boron diffusion and corresponding I-V characteristics in comparison with Si-control JFET.

• 센서학회지
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• 제9권3호
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• pp.177-181
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• 2000

턴널링 전류는 전극사이의 거리에 지수적으로 비례한다. 따라서 턴널링 전류의 변화측정을 통하여 전극간격의 미세변위를 측정할 수 있다. 본 실험에서는 micro-tip과 membrane사이에 턴널링 전류가 흐르는 피라미드형 실리콘 턴널링소자를 micro-electro-mechanical systems (MEMS) 공정을 이용하여 제조하였다. 단결정 실리콘을 KOH 용액안에서 이방성 에칭 시켜 micro-tip을 제조하였으며, 이때 $SiO_2$막을 마스크로 사용하였다 $Si_3N_4$막으로 membrane을 형성하였다. 마스크 방향에 따른 에칭 진행과정의 차이를 조사하였으며 membrane으로 사용한 $Si_3N_4$막의 stiffness를 측정하였다. 실험으로 측정하기 어려운 영역의 $Si_3N_4$막 stiffness 예측을 위한 모델식을 제시하였다.

• E2M - 전기 전자와 첨단 소재
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• 제9권2호
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• pp.188-195
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• 1996

The AlSi etching process using the MERIE type reactor carried out with different process parameters such as C1$_{2}$ and N$_{2}$ gas flow rate, RF power and chamber pressure. The etching characteristics were evaluated in terms of etch rate, selectivity, uniformity and etched profile. As the N2 gas flow rate is increased, the AlSi etch rate is decreased and uniformity has remained constant within .+-.5%. The etch rate is increased and uniformity is decreased, according to increment of the C1$_{2}$ gas flow rate, RF power and chamber pressure. Selective etching of TEOS with respect to AlSi is decreased as the RF power is increased while it is increased by increment of the C1$_{2}$ gas flow rate and chamber pressure, on the other hand, selective etching of photoresist with respect to AlSi is increased by increment of the C1$_{2}$ gas flow rate and chamber pressure, it is decreased as the N$_{2}$ gas flow rate is increased.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.847-853
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• 2016

Applications of Si have been increasingly exploited and extended to More-Moore, More-than-Moore, and beyond-CMOS approaches. Ge is regarded as one of the supplements for Si owing to its higher carrier mobilities and peculiar band structure, facilitating both advanced and optical applications. As an emerging metal-oxide device, the junctionless field-effect transistor (JLFET) has drawn considerable attention because of its simple process, less performance fluctuation, and stronger immunity against short-channel effects due to the absence of anisotype junctions. In this study, we investigated lateral field scalability, which is equivalent to channel-length scaling, in Si and Ge JLFETs. Through this, we can determine the usability of Si CMOS and hypothesize its replacement by Ge. For simulations with high accuracy, we performed rigorous modeling for ${\mu}_n$ and ${\mu}_p$ of Ge, which has seldom been reported. Although Ge has much higher ${\mu}_n$ and ${\mu}_p$ than Si, its saturation velocity ($v_{sat}$) is a more determining factor for maximum $I_{on}$. Thus, there is still room for pushing More-Moore technology because Si and Ge have a slight difference in $v_{sat}$. We compared both p- and n-type JLFETs in terms of $I_{on}$, $I_{off}$, $I_{on}/I_{off}$, and swing with the same channel doping and channel length/thickness. $I_{on}/I_{off}$ is inherently low for Ge but is invariant with $V_{DS}$. It is estimated that More-Moore approach can be further driven if Si is mounted on a JLFET until Ge has a strong possibility to replace Si for both p- and n-type devices for ultra-low-power applications.

• 대한금속재료학회지
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• 제47권11호
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• pp.748-753
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• 2009

The surface morphology and the surface roughness of n-type SiC induced by wet-treatment using 45% KOH and buffered oxide etchant (BOE-1HF : $6H_2O$) were investigated by atomic force microscopy (AFM). While Si-face of SiC could be etched by alkali solutions such as KOH, acidic solutions such as BOE were hardly able to etch SiC. When the rough SiC samples were used, the surface roughness of etched sample was decreased after wet-treatment regardless of etchant, due to the planarization the of surface by widening of scratches formed by mechanical polishing. It was observed that the initial etching was affected by the energetically unstable sites, such as dangling bond and steps. However, when a relatively smooth sample was used, the surface roughness was rapidly increased after treatment at $180^{\circ}C$ for 1 hr and at room temperature for 4 hr by using KOH solution, resulting from the nano-sized structures such as pores and bumps. This indicates that porous SiC surface can be achieved by using purely chemical treatment.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권1호
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• pp.1-7
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• 2000

The SNOSFET memory devices with ultrathin ONO(tunnel oxide-nitride-blocking oxide) gate dielectric were fabricated using n-well CMOS process and investigated its characteristics. The thicknesses of tunnel oxide, nitride and blocking oxide were $23{\AA},\; 53{\AA}\; and\; 33{\AA}$, respectively. Auger analysis shows that the ONO layer is made up of $SiO_2(upper layer of blocking oxide)/O-rich\; SiO_x\N\_y$. It clearly shows that the converting layer with $SiO_x\N\_y(lower layer of blocking oxide)/N-rich SiO_x\N\_y(nitride)/O-rich SiO_x\N\_y(tunnel oxide)$. It clearly shows that the converting layer with $SiO_x\N\_y$ phase exists near the interface between the blocking oxide and nitride. The programming condition of +8 V, 20 ms, -8 V, 50 ms is determined and data retention over 10 years is obtained. Under the condition of 8 V programming, it was confirmed that the modified Fowler-Nordheim tunneling id dominant charge transport mechanism. The programmed threshold voltage is distributed less than 0.1 V so that the reading error of memory stated can be minimized. An $8\times8$ NAND type flash EEPROM with SONOSFET memory cell was designed and simulated with the extracted SPICE parameters. The sufficient read cell current was obtained and the upper limit of $V_{TH}$ for write state was over 2V.

• 한국세라믹학회지
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• 제38권10호
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• pp.871-875
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• 2001

Cobalt silicidation at sidewall spacer edge of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) with post annealing treatment for capacitor forming process has been investigated as a function of dopant species. Cobalt silicidation of nMOSFET with n-type Lightly Doped Drain (LDD) and pMOSFET with p-type LDD produces a well-developed cobalt silicide with its lateral growth underneath the sidewall spacer. In case of pMOSFET with n-type LDD, however, a void is formed at the sidewall spacer edge with no lateral growth of cobalt silicide. The void formation seems to be due to a retarded silicidation process at the LDD region during the first Rapid Thermal Annealing (RTA) for the reaction of Co with Si, resulting in cobalt mono silicide at the LDD region. The subsequent second RTA converts the cobalt monosilicide into cobalt disilicide with the consumption of Si atoms from the Si substrate, producing the void at the sidewall spacer edge in the Si region. The void formed at the sidewall spacer edge serves as a resistance in the current-voltage characteristics of the pMOSFET device.

• 대한전자공학회논문지
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• 제3권2호
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• pp.2-9
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• 1966

실리콘 프래너트 npn 랜짓스터 제작과정을 기술하였다. 표면처리, 산화, K.P.R. boron 확산, 인확산 및 Al 증착등은 중요한 과정들이다. Boron층은 box method로 B2O3-SiO2계확산물을 사용하여 만들었고 린은 P2O5-SiO2계확산물을 사용하였다. 이 중간과정으로서 "실리콘·프래너·다이오드"도 제작되었다.

• 한국재료학회지
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• 제11권2호
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• pp.71-75
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• 2001

The reaction stability of nickel with side-wall materials of SiO$_2$ and Si$_3$N$_4$ on p-type 4"(100) Si substrate were investigated. Ni on 1300 $\AA$ thick SiO$_2$ and 500 $\AA$ - thick Si$_3$N$_4$ were deposited. Then the samples were annealed at 400, 500, 750 and 100$0^{\circ}C$ for 30min, and the residual Ni layer was removed by a wet process. The interface reaction stability was probed by AES depth Profiling. No reaction was observed at the Ni/SiO$_2$ and Ni/Si$_3$N$_4$, interfaces at 400 and 50$0^{\circ}C$. At 75$0^{\circ}C$, no reaction occurred at Ni/SiO$_2$ interface, while $NiO_x$ and Si$_3$N$_4$ interdiffused at Ni/Si$_3$N$_4$ interface. At 100$0^{\circ}C$, Ni layers on SiO$_2$ and Si$_3$N$_4$ oxidized into $NiO_x$ and then $NiO_x$ interacted with side-wall materials. Once $NiO_x$ was formed, it was not removed in wet etching process and easily diffused into sidewall materials, which could lead to bridge effect of gate-source/drain.