• 대한전자공학회논문지
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• 제22권4호
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• pp.24-32
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• 1985

This paper presents the design method for multivalued logic functions using $I^2L$ circuits. First, the a비orithm that transforms delta functions into discrete functions of a truncated difference is obtained. The realization of multivalued logic circuits by this algorithm is discussed. And then, the design method is achieved by mixing discrete functions and delta functions using the modified algorithm for given multivalued truth tables. The techniques discussed here are easily extended to multi-input and multi-output logic circuits.

• 한국수학교육학회지시리즈B:순수및응용수학
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• 제4권1호
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• pp.19-26
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• 1997

In this paper, we characterize the existence of fixed points of a multivalued function by the existence of complete preorder on the given domain. Also we investigate relations between the completeness of a given order and the fixed point property of some multivalued functions.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.278-281
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• 1988

This paper realizes the multi-output truncated difference circuits using current mode CMOS, and presents the algorithm designing multi - valued logic functions of a given multivalued truth tables. This algorithm divides the discrete valued functions and the interval functions, and transforms them into the truncated difference functions. The transformed functions are realized by current mode CMOS. The technique presented here is applied to MOD4 addition circuit and GF(4) multiplication circuit.

• 대한전자공학회논문지
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• 제15권5호
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• pp.29-33
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• 1978

본 논문에서는 Galois 스윗칭함수를 구하기 위해서 임의의 유한체상에서 정의되는 Galois 체의 성질을 설명하였고, 임의의 유한체상에서의 연산방법을 밝혔다. 고리고 Lagrange 보간법에 의한 다항식이 유한체상에서 전개될 수 있음을 증명하였다 이 결과를 적용하여 단일변수를 갖는 Galois스윗칭 함수를 유도하고 다치논리회로를 실현하였다.

• East Asian mathematical journal
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• 제24권2호
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• pp.161-168
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• 2008

We revisit the study of finding solutions of equations containing a differentiable and a continuous term on a Banach space setting [1]-[5], [9]-[11]. Using more precise majorizing sequences than before [9]-[11], we provide a semilocal convergence analysis for the generalized Newton's method as well the generalized modified Newton's method. It turns out that under the same or even weaker hypotheses: finer error estimates on the distances involved, and an at least as precise information on the location of the solution can be obtained. The above benefits are obtained under the same computational cost.

• 대한수학회논문집
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• 제9권3호
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• pp.547-564
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• 1994

Let X be a real Banach space. We consider the existence of solutions of the abstract nonlinear functional evolution equation : $$ (E) \frac{du(t)}{dt} + A(t)u(t) + F(u)(t) \ni h(t), $$ $$ u(s) = x_o \in D(A(s)), 0 \leq s \leq t \leq T, $$ where u : $[s, T] \to x$ is an unknown function, ${A(t) : 0 \leq t \leq T}$ is a given family of nonlinear (possibly multivalued) operators in X, and $F : C([s, t];X) \to L^{\infty}([s, X];X)$ and $h : [s, T] \to X$ are given functions.

• 한국통신학회논문지
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• 제13권5호
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• pp.411-421
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• 1988

본 논문에서는 Tabular法을 이용한 CCD(charge-coupled device) 4値論理回路를 설계하는 방법을 제시하였다. 첫 번째 4値 논리함수를 수산(手算) 및 컴퓨터 프로그래밍에 의해서 분해하고 이것을 기초로 하여 Tabular法에 의한 CCD 4値회로를 실현시키는 알고리즘을 유도하였다. 이 알고리즘에 의해서 2變數 4値 논리함수를 분해(分解)해서 4개의 기본게이트에 의해서 CCD회로를 실현시켰다. 본 논문의 방법에 의하면 기존방법에 비해 동일한 함수를 실현시키는데 소자수(素子數)와 코스트가 상당히 감소됨이 밝혀졌다.

• 대한전자공학회논문지
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• 제27권12호
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• pp.1878-1888
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• 1990

In this paper, the input-output interconnection method of the multi-valued signal processing circuit using perfect Shuffle technique and Kronecker product is discussed. Using this method, the design method of circuit of the multi-valued Reed-Muller expansions(MRME) to be used the multi-valued signal processing on finite field GF(p**m) is presented. The proposed input-output interconnection method is shown that the matrix transform is efficient and that the module structure is easy. The circuit design of MRME on FG(p**m) is realized following as` 1) contructing the baisc gates on GF(3) by CMOS T gate, 2) designing the basic cells to be implemented the transform and inverse transform matrix of MRME using these basic gates, 3) interconnecting these cells by the input-output interconnecting method of the multivalued signal processing circuits. Also, the circuit design of the multi-valued signal processing function on GF(3\ulcorner similar to Winograd algorithm of 3x3 array of DFT (discrete fourier transform) is realized by interconnection of Perfect Shuffle technique and Kronecker product. The presented multi-valued signal processing circuits that are simple and regular for wire routing and posses the properties of concurrency and modularity are suitable for VLSI.