• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1997.11a
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• pp.220-223
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• 1997

다치 논리는 2치 논리에 비하여 동일 정보량을 처리하는데, 고속 처리가 가능하고, 정보의 기억 밀도가 크며, 논리 회로 실현시 입.출력 단자수가 감소하는 등의 장점을 가지고 있다. 본 논문에서는 이러한 다치 논리가 가지는 장점을 이용하여, 영상 처리시 필요한 농도를 2치가 아닌 다치로 농도표현을 하고자 한다.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1998.10a
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• pp.296-299
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• 1998

본 논문은 화상처리에 다치를 이용하여 농도처리하는 방법을 제안한다. 화상처리시에 필요한 물체의 농도를 다치로 표현한 후 그 특징을 추출하고, 원영상에 대한 주요 모양 특징들을 구한다. 그리고 다치 신경망을 이용하여 학습을 시킨 후 인식하려고 하는 영상에 대한 정보의 중복성과 인식에 필요한 시간 및 기억공간을 최소화 할 수 있다.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2002.12a
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• pp.493-496
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• 2002

감정은 상당히 애매 모호하고 불명확하며 상대방의 감정을 이해하는 것은 매우 어렵다. 본 논문에서는 Plutchik의 감정 모델을 기호 다치 논리 함수의 미분을 이용하여 감정의 변화과정을 추론하는 방법을 제안한다.

• Journal of Semiconductor Engineering
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• v.1 no.1
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• pp.57-63
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• 2020

Complementary metal-oxide-semiconductor (CMOS) technology is now facing a power scaling limit to increase integration density. Since 1970s, multi-valued logic (MVL) has been considered as promising alternative to resolve power scaling challenge for increasing information density up to peta-scale level by reducing the system complexity. Over the past several decades, however, a power-scalable and mass-producible MVL technology has been absent so that MVL circuit and system implementation have been delayed. Recently, compact MVL device researches incorporating multiple-switching characteristics in a single device such as 2D heterojunction-based negative-differential resistance (NDR)/transconductance (NDT) devices and quantum-dot/superlattices-based constant intermediate current have been actively performed. Meanwhile, wafer-scale, energy-efficient and variation-tolerant ternary-CMOS (T-CMOS) technology has been demonstrated through commercial foundry. In this review paper, an overview for MVL development history including recent studies will be presented. Then, the status and its future research direction of MVL technology will be discussed focusing on the T-CMOS technology for peta-scale information processing in semiconductor chip.

• The Transactions of the Korea Information Processing Society
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• v.4 no.7
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• pp.1851-1864
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• 1997

This paper presents an algorithm simplifying the ESOP function by several rules. The algorithm is repeatedly performing operations based on the state of each terms by the product transformation operation of two functions and thus it is simplifying the ESOP function through the reduction of the product terms. Through the minimization of the product terms of the multi-valued input binary multi-output function, an optimization of the input has been done using EXOR PLA with input decoder. The algorithm when applied to four valued arithmetic circuit has been used for a EXOR logic circuit design and the two bits input decoder has been used for a EXOR-PLA design. It has been found from a computer simulation(IBM PC486) that the suggested algorithm can reduce the product terms of the output function remarkably regardless of the number of input variables when the variable AND-EXOR PLA is applied to the poperation circuit.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.3
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• pp.31-39
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• 1990

An optimization problem of AND-EXOR PLA's with input decoders can be regarded as a minimization problem of Exclusive-Or Sum-Of-Products expressions (ESOP's) for multiple-valued input two-valued output functions. In this paper, We propose a minimization algorithm for ESOP's. The algorithm is based on an iterative improvement. Five rules are used to replace a pair of products with another one. We minimized many ESOP's for arithmetic circuits. In most cases, ESOP's required fewer products than SOP's to realized same functions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.1
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• pp.76-82
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• 2002

This paper presents a quaternary-binary decoder, a quaternary logic current buffer, and a quaternary logic full-adder using current-mode multiple-valued logic CMOS circuits. Proposed full-adder requires only 15 MOSFET, 60.5% and 48.3% decrease of devices are achieved compared with conventional binary CMOS full-adder and Current's full-adder. Therefore, decrease of area and internal nods are achieved. Designed circuits are simulated and verified by HSPICE. Proposed full-adder has 1.5 ns of propagation delay and 0.42㎽ of power consumption. Also, proposed full-adder can easily adapted to binary system by use of encoder, designed decoder and designed current buffer.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.7
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• pp.78-91
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• 1998

This paper presents modular design techniques of multiple-valued logic functions about the function decomposition method and input variable management method. The function decomposition method takes avantage of the property of the column multiplicity in a single-column variable partitioning. Due to the increased number of identical modules, we can achieve a simpler circuit design by using a single T-gate, which can eliminate some of the control functions in the module libraty types. The input variable management method is to reduce the complexity of the input variables by proposing the look up table which assign input variables to a code. In this case as the number of sub-functions increase the code-length and the size of the code-assignment table grow. We identify some situations where shard input variables among sub-functions can be further reduced by a simplicication technique. According to the result of adapting this method to a function, we have demonstrated the superiority of the proposed methods which is bing decreased to about 12% of interconnection and about 16% of T-gate numbers compare with th eexisting for th enon-symmetric and irregular function realization.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.135-143
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• 2003

This paper describes the design techniques of the data converters for Multiple-Valued Logic(MVL). A 3.3V low power 4 digit CMOS analog to quaternary converter (AQC) and quaternary to analog converter (QAC) mainly designed with the neuron MOS down literal circuit block has been introduced. The neuron MOS down literal architecture allows the designed AQC and QAC to accept analog and 4 level voltage inputs, and enables the proposed circuits to have the multi-threshold properity. Low power consumption of the AQC and QAC are achieved by utilizing the proposed architecture.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.793-794
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• 2011

This paper presents a method of the circuit design of the multiple-valued digital logic switching functions based on the modular techniques. Fisr of all, we introduce the necessity, background and concepts of the modular design techniques for the digital logic systems. Next, we discuss the definitions that are used in this paper. For the purpose of the circuit design for the multiple-valued digital logic switching functions, we discuss the extraction of the partition functions. Also we describe the construction method of the building block, that is called the modules, based on each partition functions. And we apply the proposed method to the example, we compare the results with the results of the earlier methods. In result, we decrease the control functions, it means that we obtain the effective cost in the digital logic design for any other earlier methods. In the future research, we require the universal module that traet more partition functions and more compact module.