• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.05a
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• pp.338-341
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• 1998

This paper presents CMOS full adder design method based on carry-propagation-free addition trees and a circuit technique, so called multiple-valued current-nude(MVCM) circuits. The carry-propagation-free addition method uses a redundant digit sets called redundant positive-digit number representations. The carry-propagation-free addition is by three steps, and the adder can be designed directly and efficiently from the algorithm using WVCM circuit, Also Multiplier can be designed by these adder. We demonstrate the effectiveness of the proposed method through simulation(SPICE).

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2621-2624
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• 2003

In this paper, we designed 12Bit DAC(Digital to Analog Converter) that applied to multiple-valued logic system to Binary system. The proposed D/A Converter structure consists of the Binary to Quaternary Converter(BQC) and Quaternary to Analog Converter(QAC). The BQC converts the two input binary signals to the one Digit Quaternary output signal. The QAC converts the Quaternary input signal to the Analog output signal. The proposed DAC structure can implement voltage mode DAC that high resolution low power consumption with reduced chip area. And also, it has advantage of the easy expansion of resolution and fast settling time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.4
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• pp.737-745
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• 1999

In this paper, we present encoders and decoders with the two kinds of ternary Bose-Chaudhuri-Hocquenghem(BCH) codes in the most basic ternary code system from among multiple-valued code systems. One is the random-triple-error-correcting ternary BCH(26,14) code for sequential data, the other is random-triple -error-correcting ternary BCH (26,13) code. The encoders and the decoders realized are verified by experiment. Amount of the (26,13) decoder's hardware is about 50% of the one of the (26,14) decoder's one.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 1999.05a
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• pp.75-79
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• 1999

다치결정도(Multiple-valued Decision Diagram : MDD)와 순서화된 다치결정도(Ordered MDD : OMDD)는 다치논리함수의 표현에 폭넓게 사용된다. p치 n변수 인 경우 p$^{(n-1)}$ 으로 증가하는 노드의 수는 ROMDD(Reduced OMDD)를 사용하여 현저하게 감소시킬 수 있다. 그러나 다치와 다변수의 경우에는 더욱 많은 공정을 수반하게 된다. 이러한 단점을 보완하기 위해 Honghai Jiang이 제안한 2치시스템에서의 input implict/output explicit 관계를 갖는 OVAG(Output Value Array Graph)를 사용하여 다치논리함수를 표현한다. 고리고 MDD 표현이 어려운 상황에서 MOVAG(Multi OVAG)를 사용하여 보다 쉽게 출력값을 배열하는 그래프를 이끌어 낼 수 있다. 본 논문에서는 MOVAG의 구성방법과 회로에서 MOVAG로의 변환에 대한 알고리즘을 제안하였고, 알고리즘에 의한 결과를 MDD와 비교하여 노드수 감소에 따르는 처리속도가 개선됨 을 검증하였다.

• ETRI Journal
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• v.33 no.5
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• pp.822-825
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• 2011

Level-encoded dual-rail (LEDR) has been widely used in onchip asynchronous interconnects supporting a 2-phase handshake protocol. However, it inevitably requires 2N wires for N-bit data transfers. Encoder and decoder circuits that perform an asynchronous 2-phase handshake protocol with only N wires for N-bit data transfers are presented for on-chip global interconnects. Their fundamentals are based on a ternary encoding scheme using current-mode multiple valued logics. Using 0.25 ${\mu}m$ CMOS technologies, the maximum reduction ratio of the proposed circuits, compared with LEDR in terms of power-delay product, was measured as 39.5% at a wire length of 10 mm and data rate of 100 MHz.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.5
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• pp.823-832
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• 1987

This pper presents a method for constructing multiple-valued logic sequential machines based on Galois field. First, we assign all elements in GF(2**m) to bit codes using mathematical properties of GF(2**m). Then, we realized the sequencial machine circuits with and withoutm feed-back. 1) Sequential machines with feed-back are constructed by using only MUX from state-transition diagram expressing the information of sequential machines. 2) Sequential machines without feed-back are constructed by following steps. First, we assigned states in state-transition disgram to state bit codes, then obtained state function and predecessor table explaining the relationship between present states and previous states. Next, we obtained next-state function from state function and predecessor table. Finally we realized the circuit using MUX and decoder.

• ETRI Journal
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• v.43 no.6
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• pp.978-990
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• 2021

This article presents techniques for improved estimation of symbol timing offset (STO) and carrier frequency offset (CFO) for dual-polarization (DP) orthogonal frequency division multiplex (DP-OFDM) systems. Recently, quaternion multiple-input multiple-output OFDM has been proposed for high spectral efficiency communication systems, which can flexibly explore different types of diversities such as space, time, frequency, and polarization. This article focuses on synchronization techniques for DP-OFDM systems using a cyclic prefix, where the application of quaternion algebra leads to new improved estimators. Simulations performed for DP system methods show faster reduction of STO estimator variance with a double-slope line in the logvariance line versus signal-to-noise ratio (SNR) plot compared with singlepolarization (SP) counterparts, and simulations for CFO estimates show a 3-dB gain of DP over SP estimates for same SNR values defined, respectively, for quaternion-valued or complex-valued signals. Cramer-Rao bounds for STO and CFO are derived for the synchronization methods, correlating with the observed gains of DP over SP OFDM systems.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.1
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• pp.1-11
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• 2000

We propose a predistorter to compensate for nolinear distortion induced by a high power amplifier employed in multi carrier-code division multiple access (MC-CDMA) systems. The proposed scheme rests upon the fixed point iteration (FPI) associated with the contraction mapping theorem. Unlike the predistorter based on the FPI already presented by the authors in other literatures which operates on complex-valued modulation signals, the proposed predistorter in this paper deals with real-valued FPI on modulation signal amplitudes, resulting in less complexity. Simulation results on a BPSK-modulated, 64-subcarrier synchronous MC-CDMA baseband system with a traveling wave tube amplifier in the transmitter, indicate that the proposed predistorter achieves significant improvement in terms of bit error rate and total degradation over those without the predistorter. Moreover, the proposed predistorter outperforms the complex-valued counterpart, in particular, for small output back-off levels.

• Journal of the Korean Institute of Telematics and Electronics
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• v.17 no.2
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• pp.29-36
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• 1980

This paper presents a method for constructing multiple- valued switching functions based on Galois fields. First the constructing Inethod for single- variable switching functions is developers and the results are extended to multiple- variable functions. The fundalnental Inathelnatical properties used in this paper are. (1) The sum of all elements over CF of is zero. (2) The Product of nonzero elements over GF(N) is equal to e1 for Neven, and e1( ) for N odd. With these properties, a relatlvely simple constructing method is developed, and a process for determining the coefficients of the expanded forms of switching functions is also obtained without successive multiplication of the polynomials. Some examples are given to illustrate the method.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.8
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• pp.992-997
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• 1988

A generalized coding algorithm for multiple inputs multiple-valued logic gate based on shadow-casting is proposed. Proposed algorithm can minimize the useless pixels in case the number of inputs is not 2N (N is a natural number). A detailed analysis of advantages of proposed algorithm is presented and its effectiveness is demonstrated in case of three input binary system using inputs of 8*8 data.