• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.10
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• pp.1317-1326
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• 1999

As the integration ratio and operation speed increase, it has become an important problem to estimate the dissipated power during the design procedure as a method to reduce the TTM(time to market). This paper proposed a prediction model to estimate the maximum dissipated power of a CMOS logic gate. This model uses a calculational method. It was formed by including the characteristics of MOSFETs of which a CMOS gate consists, the operational characteristics of the gate, and the characteristics of the input signals. As the modeling process, a maximum power estimation model for CMOS inverter was formed first, and then a conversion model to convert a multiple input CMOS gate into a corresponding CMOS inverter was proposed. Finally, the power model for inverter was applied to the converted result so that the model could be applied to a general CMOS gate. For experiment, several CMOS gates were designed in layout level by $0.6{\mu}m$ layout design rule. The result by comparing the calculated results with those from HSPICE simulations for the gates showed that the gate conversion model has within 5% of the relative error rate to the SPICE and the maximum power estimation model has within 10% of the relative error rate. Thus, the proposed models have sufficient accuracies. Also in calculation time, the proposed models was more than 30 times faster than SPICE simulation. Consequently, it can be said that the proposed model could be used efficiently to estimate the maximum dissipated power of a CMOS logic gate during the design procedure.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.151-157
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• 2013

In this paper, a comparative analysis of PBTI induced device degradation in nanowire n-channel junctionless and inversion mode Multiple-Gate MOSFET(MuGFETs) has been performed. It has been observed that the threshold voltage is increased after PBTI stress and the threshold voltage variation of junctionless device is less significant than that of inversion mode device. However the degradation rate of junctionless device is less significant than that of inversion mode device. The activation energy of the device degradation is larger in inversion mode device than junctionless device. In order to analyze the more significant PBTI induced device degradation in inversion mode device than junctionless device, 3-dimensional device simulation has been performed. The electron concentration in inversion mode device is equal to the one in junctionless device but the electric field in inversion mode device is larger than junctionless device.

• Ecology and Resilient Infrastructure
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• v.5 no.4
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• pp.276-284
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• 2018

In order to analyze sediment transport characteristics of knickpoint migration, sediment transport length, and sediment transport weight through the under-flow type vertical lift gate, the hydraulic model experiment and dimensional analysis were performed. The correlations between Froude number and sediment transport characteristics were schematized. The multiple regression formulae for sediment transport characteristics with non-dimensional parameters were suggested. The determination coefficients of multiple regression equations appeared high as 0.618 for knickpoint migration, 0.632 for sediment transport length, and 0.866 for sediment transport weight. In order to evaluate the applicability of the developed hydraulic characteristic equations, 95% prediction interval analysis was conducted on the measured and the calculated by multiple regression equations, and it was determined that NSE (Nash-Sutcliffe Efficiency), RMSE (root mean square), and MAPE (mean absolute percentage error) are appropriate, for the accuracy analysis related to the prediction on sediment transport characteristics of kickpoint migration, sediment transport length and weight.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.859-862
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• 2003

This paper proposes an emulation environment for SoC designs using small number of large gate-count FPGA's and a PC system. To overcome the pin limitation problem in partitioning the design when the design size overwhelms the FPGA gate count, we use bus splitter modules that replicate on-chip bus signals in one FPGA to arbitrary number of other FPGA's with minimal pin count. The proposed scheme is applied to the emulation of 2 million gate multimedia processing chip using two Xilinx Viretex-2 6000 FPGA devices in 6.6MHz operating frequency. An ARM core, memories, camera and LCD display are modeled in software using dual 2GHz Pentium-III processors. This scheme can be utilized for more than 2 FPGA's in the same ways as two FPGA case without losing emulation speed.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.148-150
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• 2009

We have developed 15 inch, 130 blocks local dimming FEL using printed CNT emitters, in which multiple FE blocks were built with a common gate electrode. Cathode electrode formed by the double-metal technique, in which an insulator is interposed between the addressing bus and cathode electrode.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.115-122
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• 2004

In this paper, the multiple-valued adders and multipliers are implemented by current-mode CMOS. First, we implement the 3-valued T-gate and the 4-valued T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second we implement the circuits to be realized 2-variable 3-valued addition table and multiplication table over finite fields $GF(3^2)$, and 2-variable 4-valued addition table and multiplication table over finite fields $GF(4^2)$ with the multiple-valued T-gates. Finally, these operation circuits are simulated under $1.5\mutextrm{m}$ CMOS standard technology, $15\mutextrm{A}$ unit current, and 3.3V VDD voltage Spice. The simulation results have shown the satisfying current characteristics. The 3-valued adder and multiplier, and the 4-valued adder and multiplier implemented by current-mode CMOS is simple and regular for wire routing and possesses the property of modularity with cell array. Also, since it is expansible for the addition and multiplication of two polynomials in the finite field with very large m, it is suitable for VLSI implementation.

• Transactions on Electrical and Electronic Materials
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• v.10 no.2
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• pp.35-39
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• 2009

A novel Helmholtz coil inductively coupled plasma(H-ICP) etcher is proposed and characterized for deep nano-scale CMOS technology. Various hardware tests are performed while varying key parameters such as distance between the top and bottom coils, the distance between the chamber ceiling and the wafer, and the chamber height in order to determine the optimal design of the chamber and optimal process conditions. The uniformity was significantly improved by applying the optimum conditions. The plasma density obtained with the H-ICP source was about $5{\times}10^{11}/cm^3$, and the electron temperature was about 2-3 eV. The etching selectivity for the poly-silicon gate versus the ultra-thin gate oxide was 482:1 at 10 sccm of $HeO_2$. The proposed H-ICP was successfully applied to form multiple 60-nm poly-silicon gate layers.

• Korean Institute of Interior Design Journal
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• v.17 no.5
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• pp.72-79
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• 2008

Nagaya is one of the traditional Japanese housing types in which multiple houses are attached together. In Nagaya, walls are shared by several houses but entrances are privately owned by houses. Nagaya consists of many wooden houses for common people located in parallel with narrow alleys between them. Nagaya was one of the representative housing types in Japanese architectural history. This research is to study the background of the origination of Nagaya in Japan, the characteristics of space and land planning, the features and causes of the changes in the space and land planning. In this research, we observed and analyzed unit plans of a block of gate-type Nagayas in Hanan, Osaka. The results are as follows. First, as the inner alleys(Roji) are closed, the number of entrances to each housing lot decreased from two to one since one entrance that used to be open to inner alleys(Roji) are permanently closed. Second, walls between streets and housing lots which used to be one of the outstanding characteristics of gate-type Nagayas are disappearing. Third, as the bathrooms are added to houses, the front gardens are being degraded to empty spaces or sometimes totally removed. Fourth, the space in the first floor of houses become family spaces, and that in the second floor is divided into private rooms for individuals.

• Journal of Korean Institute of Industrial Engineers
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• v.29 no.2
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.5 no.1
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• pp.91-100
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• 1985

This study is on the gate operation of dams, which are for the hydropower and multipurpose in Han River Basin, considering the safety under the emergency. The results of the study on the safety of dams in Han River Basin associated with the gate operation of dams against the design flood flow and the combined inflow are as follows; 1) The empirical formula (1) can be used for gate operation with the informations of reservoir's water level and the inflow. 2) The applicability of the multiple regression formula (2) among the gate opening area, inflow, water level, and outflow is assured. 3) From the safety analysis of dams for the emergency by the procedures developed in this study, six dams are safe except Soyanggang, Euiam, and Cheongpyung Dam, but the above three dams can be safe with the lowering of the starting water level of gate opening by the pre-discharges.