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Classifying Rules by In-out Traffic Direction to Avoid Security Policy Anomaly

  • Kim, Sung-Hyun;Lee, Hee-Jo
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.4 no.4
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    • pp.671-690
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    • 2010
  • The continuous growth of attacks in the Internet causes to generate a number of rules in security devices such as Intrusion Prevention Systems, firewalls, etc. Policy anomalies in security devices create security holes and prevent the system from determining quickly whether allow or deny a packet. Policy anomalies exist among the rules in multiple security devices as well as in a single security device. The solution for policy anomalies requires complex and complicated algorithms. In this paper, we propose a new method to remove policy anomalies in a single security device and avoid policy anomalies among the rules in distributed security devices. The proposed method classifies rules according to traffic direction and checks policy anomalies in each device. It is unnecessary to compare the rules for outgoing traffic with the rules for incoming traffic. Therefore, classifying rules by in-out traffic, the proposed method can reduce the number of rules to be compared up to a half. Instead of detecting policy anomalies in distributed security devices, one adopts the rules from others for avoiding anomaly. After removing policy anomalies in each device, other firewalls can keep the policy consistency without anomalies by adopting the rules of a trusted firewall. In addition, it blocks unnecessary traffic because a source side sends as much traffic as the destination side accepts. Also we explain another policy anomaly which can be found under a connection-oriented communication protocol.

The Development of the Standards of Performance Assessment for an Affective Domain of Mathematics in High School (고등학교 수학의 정의적 영역에 대한 수행평가 기준 개발)

  • 이종연
    • School Mathematics
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    • v.4 no.2
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    • pp.193-204
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    • 2002
  • Performance assessment has been introduced to school education as an alternative measure of the former educational assessment which put much emphasis on the result rather than the process of learning, memorization than pursuit of knowledge, and passive than active study. As for the subject of mathematics, the change of the assessment came to replace multiple choice tests with descriptive- and statement-type tests. This means animprovement on the testing system, focusing on the process of finding out the answer. The main focus, however, is still on the intellectual domain without paying due attention to the emotional domain of mathematics education. The previous studies on the assessment of emotional domain In mathematics have shown that there are stumbling blocks in the application of the assessment, such as the disputes on the reliability, objectivity, and fairness as well as the complicated procedure of applying the results to school records. The lack of the development and supply of the appropriate assessment tools have also been pointed out. Therefore, this study has been carried out with the intention of establishing an applicable standard of assessment on the emotional domain of high school matematics. As a result, detailed standards of performance assessment, which adopt oral examination, discussion, observation, and report have been developed. The problems which are likely to emerge In the course of the application of the newly developed assessment are under study as a continuing research project.

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A Block Replacement Scheme using Analytic Hierarchy Process in Hybrid HDD (하이브리드 하드디스크에서 AHP를 적용한 블록 교체 기법)

  • Kim, Jeong-Won
    • Journal of Korea Society of Industrial Information Systems
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    • v.20 no.5
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    • pp.45-52
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    • 2015
  • The read performance of hybrid hard disk is better than the legacy hard disk and power consumption is also considerably low. As blocks with enough localities may be located in the non-volatile cache whose size is generally limited, an effective block replacement scheme is required. As this replacement is inevitably affected by various parameters, we define this issue as a kind of multiple criteria decision model. To solve this problem, this paper suggests a new block replacement algorithm based on the analytic hierarchy process. Through simulation for our model, we confirmed that the proposed model could be used as a replacement algorithm of the hybrid hard disk as it may improve boot time as well as response time of general applications.

Stellate Ganglion Block for Treatment of Central Serous Chorioretinopathy (중심성 장액 맥락망막증의 성상신경절 차단요법 1예)

  • Kim, Chang-Sung;Park, Chong-Min;Suh, Jae-Hyun;Kim, Sung-Nyeun
    • The Korean Journal of Pain
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    • v.8 no.2
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    • pp.324-327
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    • 1995
  • Central serous chorioretinopathy is a relatively benign condition of young to middle-aged men, characterized by serous detachment of central retina as a consequence of focal leakage of fluid from the choriocapillaris through a defect in the retinal pigment epithelium. Approximately 80% of central serous chorioretinopathy undergo spontaneous resolution within 6 months. However 20 to 30% of patients with central serous chorioretinopathy have one or more recurrences and undergo chronic courses. In these cases laser photocoagulation is used to burn the leakage site directly, but there is no evidence that it reduces the chance of permanent loss of visual function and recurrence. We have administered stellate ganglion blocks (SGB) on a 43 year old male patient with central serous chorioretinopathy with multiple recurrences and experienced good results. We therefore recommend SGB as an effective treatment for central serous chorioretinopathy in conjunction with other ophthalmological treatments.

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Yield Enhancement Techniques for 3D Memories by Redundancy Sharing among All Layers

  • Lee, Joo-Hwan;Park, Ki-Hyun;Kang, Sung-Ho
    • ETRI Journal
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    • v.34 no.3
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    • pp.388-398
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    • 2012
  • Three-dimensional (3D) memories using through-silicon vias (TSVs) will likely be the first commercial applications of 3D integrated circuit technology. A 3D memory yield can be enhanced by vertical redundancy sharing strategies. The methods used to select memory dies to form 3D memories have a great effect on the 3D memory yield. Since previous die-selection methods share redundancies only between neighboring memory dies, the opportunity to achieve significant yield enhancement is limited. In this paper, a novel die-selection method is proposed for multilayer 3D memories that shares redundancies among all of the memory dies by using additional TSVs. The proposed method uses three selection conditions to form a good multi-layer 3D memory. Furthermore, the proposed method considers memory fault characteristics, newly detected faults after bonding, and multiple memory blocks in each memory die. Simulation results show that the proposed method can significantly improve the multilayer 3D memory yield in a variety of situations. The TSV overhead for the proposed method is almost the same as that for the previous methods.

Partially BTIB Designs for Comparing Treatments with a Control (처리(處理)들과 대조(對照)와의 비교(比較)를 위한 부분(部分)BTIB실험계획모형(實驗計劃模型))

  • Kim, Kwang-Hun
    • Journal of the Korean Data and Information Science Society
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    • v.1
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    • pp.7-33
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    • 1990
  • Bechhofer and Tamhane(1981) developed a theory of optimal incomplete block designs for comparing several treatments with a control. This class of designs is appropriate for comparing simultaneously $p{\geq}2$ test treatments with a control treatment (the so-called multiple comparisons with a control (MCC) problem) when the observations are taken in incomplete blocks of common size $K{\<}p+1$. In this paper we want to extend to partially BTIB designs with two associate classes for the MCC problem. We propose a new class of incomplete block designs that are partially balanced with respect to test treatments. Because the class of designs that we consider is larger than the class of designs in Bechhofer and Tamhane and provides us with designs that improve on the optimal designs in their class. We shall use the abbreviation PBTIB to refer to such designs. We study their structure and give some methods of construction. Also we describe a procedure for making exact joint confidence statements for the MCC problem in PBTIB Designs with two associate classes. We study Optimality, Admissibility considerations in PBTIB designs with two associate classes.

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Multi-code Biorthogonal Code Keying with Constant Amplitude Coding using Interleaving and $Q^2PSK$ for maintaining a Constant Amplitude feature and increasing Bandwidth Efficiency (정 진폭 부호화된 Multi-code Biorthogonal Code Keying 시스템에서 인터리빙과 $Q^2PSK$를 이용하여 정 진폭 특성을 유지하면서 대역폭 효율을 개선시키는 방안)

  • Kim, Sung-Pil;Kim, Myoung-Jin
    • 한국정보통신설비학회:학술대회논문집
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    • 2005.08a
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    • pp.427-430
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    • 2005
  • A multi-code biorthogonal code keying (MBCK) system consists of multiple waveform coding blocks, and the sum of output codewords is transmitted. Drawback of MBCK is that it requires amplifier with high linearity because its output symbol is multi-level. MBCK with constant amplitude precoding block (CA-MBCK) has been proposed, which guarantees sum of orthogonal codes to have constant amplitude. The precoding block in CA-MBCK is a redundant waveform coder whose input bits are generated by processing the information bits. Redundant bits of constant amplitude coded CA-MBCK are not only used to make constant amplitude signal but also used to improve the BER performance at the receiver. In this paper, we proposed a transmission scheme which combines CA-MBCK with $Q^2PSK$ modulation to improve bandwidth efficiency of CA-MBCK and also uses chip interleaving to maintain a constant amplitude feature of CA-MBCK. bandwidth efficiency of a proposed transmission scheme is increased fourfold. And the BER performance of the scheme is same as that of CA-MBCK.

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A New Driving Method for Gray-scale Expression in an AC Plasma Display Panel (교류형 플라즈마 디스플레이 패널에서 계조표현을 위한 새로운 구동방식)

  • 김재성;황현태;서정현;이석현
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.53 no.8
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    • pp.407-414
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    • 2004
  • In this paper, a new gray scale expression method that divides the scan lines into multiple blocks is suggested. The proposed method can drive 16 sub-fields per 1 TV field in the panel with XGA ($1366{\times}768$) resolution. The on and off states of even subfields depend on the condition of odd subfields. The write address mode is used in the odd subfields, while the erase address mode is used in the even subfields. Because the ramp reset pulse is applied every 2 sub-fields, both the contrast ratio and the dynamic voltage margin are sufficiently obtained in comparison with previous AWD (Address While Display) methods. In realizing 16 subfields, shortening the scan time in the erase address period was important. The X bias voltage in the erase address period affected the minimum address voltage but did not the delay time of the address discharge. The delay time of the address discharge was affected by the address voltage and the time interval between the last sustain discharge and the scanning time. We also evaluated the dynamic false contour. New method shows an improved image quality in horizontal moving, but discontinuous lines were observed at the boundaries of each block in vertical moving

Long-run Equilibrium Relationship Between Financial Intermediation and Economic Growth: Empirical Evidence from Philippines

  • MONSURA, Melcah Pascua;VILLARUZ, Roselyn Mostoles
    • The Journal of Asian Finance, Economics and Business
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    • v.8 no.5
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    • pp.21-27
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    • 2021
  • The financial sector is one of the most important building blocks of the economy. When this sector efficiently implemented a well-crafted program on banking and financial system to translate financial activities to income-generating activity, economic growth will be realized. Hence, this study analyzed the effect of financial intermediation on economic growth and the existence of cointegrating relationship using time-series data from 1986 to 2015. The influence of financial intermediation in terms of bank credit to bank deposit ratio, private credit, and stock market capitalization and time trend to economic growth was estimated using ordinary least squares (OLS) multiple regression. The results showed that all the financial intermediation indicators and time trend exert significant effect on Gross Domestic Product (GDP) per capita. The positive sign of the time trend indicates that there is an upward trend in GDP per capita averaging approximately 0.06 percent annually. Furthermore, the cointegration test using the Johansen procedure revealed that there is a presence of long-term equilibrium relationship between financial intermediation and time trend and economic growth, and rules out spurious regression results. This study established the idea that financial intermediation in the Philippines has a significant and vital role in stimulating growth in the economy.

Implementation of Low Complexity FFT, ADC and DAC Blocks of an OFDM Transmitter Receiver Using Verilog

  • Joshi, Alok;Gupta, Dewansh Aditya;Jaipuriyar, Pravriti
    • Journal of Information Processing Systems
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    • v.15 no.3
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    • pp.670-681
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    • 2019
  • Orthogonal frequency division multiplexing (OFDM) is a system which is used to encode data using multiple carriers instead of the traditional single carrier system. This method improves the spectral efficiency (optimum use of bandwidth). It also lessens the effect of fading and intersymbol interference (ISI). In 1995, digital audio broadcast (DAB) adopted OFDM as the first standard using OFDM. Later in 1997, it was adopted for digital video broadcast (DVB). Currently, it has been adopted for WiMAX and LTE standards. In this project, a Verilog design is employed to implement an OFDM transmitter (DAC block) and receiver (FFT and ADC block). Generally, OFDM uses FFT and IFFT for modulation and demodulation. In this paper, 16-point FFT decimation-in-frequency (DIF) with the radix-2 algorithm and direct summation method have been analyzed. ADC and DAC in OFDM are used for conversion of the signal from analog to digital or vice-versa has also been analyzed. All the designs are simulated using Verilog on ModelSim simulator. The result generated from the FFT block after Verilog simulation has also been verified with MATLAB.