• Proceedings of the KIPE Conference
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• 1997.07a
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• pp.21-26
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• 1997

Multilevel Inverter for the application of IM system is modeled, analyzed the harmonics component of output current at SIMULINK environment. In this paper Optimum of fc, M in 5-Level PWM Inverter is proposed.

• Journal of Power Electronics
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• v.14 no.2
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• pp.302-314
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• 2014

Due to advancements in power electronics and inverter topologies, the current controlled multilevel voltage-source pulse width modulated (PWM) inverter is usually preferred for accurate control, quick response and high dynamic performance. A multilevel topology approach is found to be best suited for overcoming many problems arising from the use of high power converters. This paper presents a comprehensive review and comparative study of several current control (CC) techniques for multilevel inverters with a special emphasis on various approaches of the hysteresis current controller. Since the hysteresis CC technique poses a problem of variable switching frequency, a ramp-comparator controller and a predictive controller to attain constant switching frequency are described along with its quantitative comparison. Furthermore, various methods have been reviewed to achieve hysteresis current control PWM with constant switching frequency operation. This paper complies various guidelines to choose a particular method suitable for application at a given power level, switching frequency and dynamic response.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1316-1323
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• 2016

Multilevel inverters (MLIs) have been preferred over conventional two-level inverters due to their inherent properties such as reduced harmonic distortion, lower electromagnetic interference, minimal common mode voltage, ability to synthesize medium/high voltage from low voltage sources, etc. On the other hand, they suffer from an increased number of switching devices, complex gate pulse generation, etc. This paper develops an ingenious symmetrical MLI topology, which consumes lesser component count. The proposed level dependent sources concoction multilevel inverter (LDSCMLI) is basically a multilevel dc link MLI (MLDCMLI), which first synthesizes a stepped dc link voltage using a sources concoction module and then realizes the ac waveform through a conventional H-bridge. Seven level and eleven level versions of the proposed topology are simulated in MATLAB r2010b and prototypes are constructed to validate the performance. The proposed topology requires lesser components compared to recent component reduced MLI topologies and the classical topologies. In addition, it requires fewer carrier signals and gate driver circuits.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2067-2075
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• 2016

Cascaded H-bridge multilevel inverters are currently used because it enables the integration of various sources, such as batteries, ultracapacitors, photovoltaic array and fuel cells in a single system. Conventional modulation schemes for multilevel inverters have concentrated mainly on the generation of a low harmonic output voltage, which results in less effective utilization of connected sources. Less effective utilization leads to a difference in the charging/discharging of sources, causing unsteady voltages over a long period of operation and a reduction in the lifetime of the sources. Hence, a charge balance control scheme has to be incorporated along with the modulation scheme to overcome these issues. In this paper, a new approach for charge balancing in symmetric cascaded H-bridge multilevel inverter that enables almost 100% charge balancing of sources is presented. The proposed method achieves charge balancing without any additional stages or complex circuit or considerable computational requirement. The validity of the proposed method is verified through simulation and experiments.

• Journal of Electrical Engineering and Technology
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• v.7 no.4
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• pp.538-545
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• 2012

In this paper a novel cascaded transformer multilevel inverter is proposed. Each basic unit of the inverter includes two DC sources, single phase transformers and semiconductor switches. This inverter, which operates as symmetric and asymmetric, can output more number of voltage levels in the same number of the switching devices. Besides, the number of gate driving circuits is reduced, which leads to circuit size reduction and lower power consumption in the driving circuits. Moreover, several methods to determination of transformers turn ratio in proposed inverter are presented. Theoretical analysis, simulation results using MATLAB/SIMULINK and experimental results are provided to verify the operation of the suggested inverter.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.4
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• pp.307-314
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• 2009

In this paper, we proposes a multilevel inverter which can synthesize multi output voltage levels by adding DC voltage sources and switch components. In the proposed circuit topology, full-bride inverter determines the output polarity and the number of output voltage levels are defined by the operation of the additional switches. It can reduce the number of switch devices compared with the conventional approaches when they generate the same number of output voltage levels. To verify the validity of the proposed multilevel inverter, we present simulation and experimental results using a prototype.

• Journal of international Conference on Electrical Machines and Systems
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• v.2 no.2
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• pp.190-196
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• 2013

It presents a unification of buck-boost and flyback converter for driving a cascaded H-bridge multilevel inverter with a single independent DC voltage source. Cascaded H-bridge multilevel inverter is useful to make many output voltage levels for sinusoidal waveform by combining two or more H-bridge modules. However, each H-bridge module needs an independent DC voltage source to generate multi levels in an output voltage. This topological characteristic brings a demerit of increasing the number of independent DC voltage sources when it needs to increase the number of output voltage levels. To solve this problem, we propose a converter combining a buck-boost converter with a flyback converter. The proposed converter provides independent DC voltage sources at back-end two H-bridge modules. After analyzing theoretical operation of the circuit topology, the validity of the proposed approach is verified by computer-aided simulations using PSIM and experiments.

• Transactions on Electrical and Electronic Materials
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• v.18 no.4
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• pp.229-236
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• 2017

This paper deals with the design and implementation of an efficient topology for cascaded multilevel inverters with reduced part counts. In the proposed design, a well-established basic unit is first developed. The series extension of this unit results in the formation of the proposed multilevel inverter. The proposed design minimizes the number of power electronic components including insulated-gate bipolar transistors and gate driver circuits, which in turn cuts down the size of the inverter assembly and reduces the operating power losses. An explicit control strategy with enhanced device efficiency is also acquired. Thus, the part count reductions enhance not only the economical merits but also the technical features of the entire system. In order to accomplish the desired operational aspects, three algorithms are considered to determine the magnitudes of the dc voltage sources effectively. The proposed topology is compared with the conventional cascaded H-bridge multilevel inverter topology, to reflect the merits of the presented structure. In continue, both the analytical and experimental results of a cascaded 31-level structure are analyzed. The obtained results are discussed in depth, and the exemplary performance of the proposed structure is corroborated.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1235-1243
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• 2015

This paper presents a modified Space Vector Pulse Width Modulation Technique (SVPWM), which solves the well-known problem of voltage imbalance in the capacitors of a single-phase multilevel inverter. The proposed solution is based on the measurement of DC voltage levels at each capacitor of the inverter DC bus. The measurements are then used to adjust the size of the active vectors within the SVPWM algorithm to keep the voltage waveform sinusoidal regardless of any voltage imbalance on the DC link capacitors. When a voltage deviation exceeds a predetermined hysteresis band, the correspondent voltage vector is restricted to restore the voltage level to an acceptable threshold. Hence, the need for external voltage regulators for the voltage capacitors is eliminated. The functionality of the proposed algorithm is successfully demonstrated through simulations and experiments on a grid tied application.

• Proceedings of the KIPE Conference
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• 2003.07a
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• pp.23-26
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• 2003

This paper presents a novel hybrid type multilevel inverter in order to improve the waveshape of output voltage. The proposed multilevel inverter is consist of two full-bridge modules for level creation and one full-bridge module for PWM operation. The generated levels are total 11-level: 9-level by the level inverter and 2-level by the PWM inverter. The operational principles and analysis are explained and validity of the proposed system is verified through the experimental results using a prototype.