• 제어로봇시스템학회:학술대회논문집
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• 1992.10a
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• pp.303-308
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• 1992

In this study, we propose a shared storage system which is more efficient policy than MIS(Mixed Intermediate Storage) policy for relatively rare storage system and can be called CIS(Common Intermediate Storage) policy. Using this strategy, we develop a new completion time algorithm and apply it to two kinds of optimal or near optimal scheduling method; combinatorial search and simulated annealing method. We also extend this strategy to other storage policy, for example MIS policy, with PLC(Programmable Logic Controller) logic and on/off action of electronic valves. It thus can be accepted as a basic form of FMS(Flexible Manufacturing System) for operating various storage policies. Finally we suggest the interlocking block to compansate for the shortcoming of CIS policy, i.e, complication of operation and safety, resulting in a basic batch process automation mode.

• 제어로봇시스템학회:학술대회논문집
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• 1999.10a
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• pp.61-64
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• 1999

In this paper, a technique to expand the Input and Output (I/O) of the programmable logic controller (PLC) using remote I/O module is presented. The controller and the remote I/O module should have the same protocol and are interfaced through RS 485. Each remote I/O module consists of 16 digital input and 16 digital output, and the maximum of 32 remote I/O module can be linked to one controller. The remote I/O is programmed for interrupt request to controller independently. Therefore, there is no affect to the scan time of the controller. Using this technique, the PLC can be efficiently applied to the several hundred meters different control points such as the ON-OFF control fur the agriculture farm, the building automation system, a multi group of machine control.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.1
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• pp.95-102
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• 2013

This paper covers nulling algorithm. In this algorithm, we assume that nulling points are already known. In general, nulling algorithm using matrix equation was utilized. But, this algorithm is pointed out that computational complexity is disadvantage. So, we choose gradient method to reduce the computational complexity. In order to further reduce the computational complexity, we propose approximate gradient method using characteristic of trigonometric functions. The proposed method has same performance compared with conventional method while having half the amount of computation when the number of antenna and nulling point are 20 and 1, respectively. In addition, we could virtually eliminate the trigonometric functions arithmetic. Trigonometric functions arithmetic cause a big problem in actual implementation like FPGA processor(Field Programmable gate array). By utilizing the above algorithm in a multi-cell environment, beamforming gain can be obtained and interference can be reduced at same time. By the above results, the algorithm can show excellent performance in the cell boundary.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.223-224
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• 2007

To develop nuclear measurement system with characteristics including both re-configuration and multi-functions, we proposed a field programmable gate array (FPGA) technique to implement TDC which is more suitable for high energy Physics system. In TDC scheme, the timing resolution is more important than the count rates of channel. In order to manage pico-second resolution TDC, we used the delay components of FPGA, utilized the place and route (P&R) delay difference, and then got two ring oscillators. By setting P&R area constraints, we generated two precise ring oscillators with slightly different frequencies. Finally, we evaluated that the period difference of these two ring oscillators was about 60 pico-seconds, timing resolution of TDC.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2004.11a
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• pp.365-370
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• 2004

The integration of intelligent devices, devices-level networks, and software into motor control systems can deliver improved diagnostics, fast warnings for increased system reliability, design flexibility, and simplified wiring. Remote access to motor-control information also affords an opportunity for reduced exposure to hazardous voltage and improved personnel safety during startup and trouble-shooting. This paper presents LonWorks fieldbus networked intelligent induction control system architecture. Experimental bed system with two inverter motor driving system for controlling 1.5kW induction motor is configured for LonWorks networked intelligent motor control. In recent years, MCCs have evolved to include component technologies, such as variable-speed drives, solid-state starters, and electronic overload relays. Integration was accomplished through hardwiring to a programmable logic controller (PLC) or distributed control system (DCS). Devicelevel communication networks brought new possibilities for advanced monitoring, control and diagnostics. This LonWorks network offered the opportunity for greatly simplified wiring, eliminating the bundles of control interwiring and corresponding complex interwiring diagrams. An intelligent MCC connected in device level control network proves users with significant new information for preventing or minimizing downtime. This information includes warnings of abnormal operation, identification of trip causes, automated logging of events, and electronic documentation. In order to show the application of the multi-motors control system, the prototype control system is implemented. This paper is the first step to drive multi-motors with serial communication which can satisfy the real time operation using LonWorks network.

• Journal of Sensor Science and Technology
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• v.32 no.4
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• pp.246-251
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• 2023

Internet of Things (IoT) systems process signals from various sensors using signal processing algorithms suitable for the signal characteristics. To analyze complex signals, these systems usually use signal processing algorithms in the frequency domain, such as fast Fourier transform (FFT), filtering, and short-time Fourier transform (STFT). In this study, we propose a multi-mode sensor signal processor (SSP) accelerator with an FFT-based hardware design. The FFT processor in the proposed SSP is designed with a radix-2 single-path delay feedback (R2SDF) pipeline architecture for high-speed operation. Moreover, based on this FFT processor, the proposed SSP can perform filtering and STFT operation. The proposed SSP is implemented on a field-programmable gate array (FPGA). By sharing the FFT processor for each algorithm, the required hardware resources are significantly reduced. The proposed SSP is implemented and verified on Xilinxh's Zynq Ultrascale+ MPSoC ZCU104 with 53,591 look-up tables (LUTs), 71,451 flip-flops (FFs), and 44 digital signal processors (DSPs). The FFT, filtering, and STFT algorithm implementations on the proposed SSP achieve 185x average acceleration.

• Proceedings of the Korean Society of Medical Physics Conference
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• 2002.09a
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• pp.468-470
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• 2002

We have designed X-ray detection system and multi-channel data acquisition system for Spiral CT application. X-ray detection system consists of scintillator and photodiode. Scintillator converts X-ray into visible light. Photodiode converts visible light into electrical signal. The multi-channel data acquisition system consists of analog, digital, master and backplane board. Analog board detects electrical signal and amplifies signal by 140dB. Digital board consists of MUX(Multiplex) which routes multi-channel analog signal to preamplifier, and ADC(Analog to Digital Converter) which converts analog signal into digital signal. Master board supplies the synchronized clock and transmits the digital data to image reconstructor. Backplane provides electrical power, analog output and clock signal. The system converts the projected X-ray signal over the detector array with large gain, samples the data in each channel sequentially, and the sampled data are transmitted to host computer in a given time frame. To meet the timing limitation, this system is very flexible since it is implemented by FPGA(Field Programmable Gate Array). This system must have a high-speed operation with low noise and high SNR(signal to noise ratio), wide dynamic range to get a high resolution image.

• Journal of IKEEE
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• v.24 no.1
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• pp.161-169
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• 2020

In order to reduce the manufacturing cost of MCU chips used in applications such as wireless chargers and USB-C, compared to DP-EEPROM (Double Poly EEPROM), which requires 3 to 5 additional process masks, it is even more necessary MTP(Multi-Time Programmable), which is less than one additional mask and have smaller unit cell size. In addition, in order to improve endurance characteristics and data retention characteristics of the MTP memory cell due to E/P(Erase / Program) cycling, the distribution of the V_TP(Program Threshold Voltage) and the V_TE(Erase Threshold Voltage) needs to be narrow. In this paper, we proposed a current-type BL S/A(Bit-Line Sense Amplifier) circuit, WM(Write Mask) circuit, BLD(BL Driver) circuit and a algorithm, which can reduce the distribution of program and V_T and erase V_T, through compare the target current by performing the erase and program pulse of the short pulse several times, and if the current specification is satisfied, the program or erase operation is no longer performed. It was confirmed that the 256Kb MTP memory fabricated in the Magnachip semiconductor 0.13㎛ process operates well on the wafer in accordance with the operation mode.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.4
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• pp.71-81
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• 1999

We propose a new CPLD(Complexity Programmable Logic Device) technology mapping algorithm improving run-time under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG(Directed Acyclic Graph) type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs, run-time to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB(Configurable Logic Block). In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces run-time and the number of CLBs much more than the TEMPLA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.4
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• pp.84-92
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• 2002

As today's field programmable gate arrays have very large logic capacity as well as relatively fast operation speed, they're widely used in many application areas. However, debugging the design implemented in FPGA's is very time-consuming and painful as the internal signal probing usually requires large number of FPGA re-compilations, which take tremendously long time. In this paper, we analyze the problems in FPGA debugging and propose a new powerful debugging solution. With the proposed FPGA debugging solution, we can guarantee not only to provide 100% internal signal visibility without FPGA re-compilation for the design in FPGA's, but also to identify at least one design bug per FPGA compilation. An experimental result has clearly shown the proposed approach to FPGA debugging very powerful and practical.