• Journal of Electrical Engineering and Technology
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• 제13권4호
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• pp.1638-1643
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• 2018

Multi-layer ceramic capacitors as decoupling capacitor were fabricated by dielectric composition with a high dielectric constant. The fabricated decoupling capacitors were embedded in the PCB of the 10G RF transceiver module and evaluated for the characteristics of electrical noise by the level of AC input voltage. In order to further improve the electrical properties of the $BaTiO_3$ based composite, glass frit, MgO, $Y_2O_3$, $Mn_3O$, $V_2O_5$, $BaCO_3$, $SiO_2$, and $Al_2O_3$ were used as additives. The electrical properties of the composites were determined by various amounts of additives and optimum sintering temperature. As a result of the optimized composite, it was possible to obtain a density of $5.77g/cm^3$, a dielectric constant of 1994, and an insulation resistance of $2.91{\times}10^{12}{\Omega}$ at an additive content of 5wt% and a sintering temperature of $1250^{\circ}C$. After forming a $2.5{\mu}m$ green sheet using the doctor blade method, a total of 77 layers were laminated and sintered at $1180^{\circ}C$. A decoupling capacitor with a size of $0.6mm(W){\times}0.3mm(L){\times}0.3mm(T)$ (width, length and thickness, respectively) and a capacitance of 100 nF was embedded using a PCB process for the 10G RF Transceiver modules. In the range of AC input voltage 400mmV @ 500kHz to 2200mV @ 900kHz, the embedded 10G RF Transceiver modules evaluated that it has better electrical performance than the non-embedded modules.

• 한국전기전자재료학회논문지
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• 제15권6호
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• pp.499-503
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• 2002

In this study, to develop the high power piezoelectric transformer for adaptor, PSN-PNN-PZT system ceramics were formulated as a function of $MnO_2$ addition and its dielectric and piezoelectric characteristics were investigated. Multi-layer piezoelectric transformer using an excellent composition was also fabricated and its electrical properties evaluated. The composition ceramics added to 0.5wt%$MnO_2$ showed the maximum value of $k_p=0.61$ and $Q_m=1.321$. As the output power of piezoelectric transformer is increased, its temperature rise increased. At the fixed 18W output power, the transformer was stably operated.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2009년도 추계학술대회 논문집
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• pp.153-157
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• 2009

A Highly efficient Mercury-free Flat Fluorescent Lamp (MFFL) with dielectric barrier Xe gas discharge was developed for an alternative of conventional line-type Cold Cathode Fluorescent Lamps (CCFLs) which shows a wide voltage margin and a stable discharge operation for diffuse glow discharge with an application of a auxiliary electrode. Electro-optic characteristics of the MFFL were examined through the changes in ambient temperature, total pressure and Xe partial pressure. the single cell is expanded into a multi-structured configuration to realize a large sized lamp by a simple repetition of the single cells, and a new driving scheme is proposed for an adaptive brightness control using dual auxiliary electrodes and bi-polar drive scheme. In addition, interesting application of this ultra high luminance flat lamp by the optimization of the gas condition and the pattern of the rear phosphor layer is suggested as a good alternative of daylight lamp source

• 한국광학회지
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• 제13권3호
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• pp.209-214
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• 2002

기판의 표면거칠기가 반사경의 산란에 미치는 영향을 조사하였다. 기판의 표면거칠기가 다른 다섯 종류의 기판에 이온빔 스퍼터링 방법과 전자총 증착 방법으로 각각 반사율이 1에 가까운 고반사율 박막을 증착하고 산란을 TIS 방법으로 측정하였다. 기판의 표면거칠기가 2$\AA$ 이상인 경우의 기판의 산란에 대한 반사경 산란 비율은 표면거칠기가 2$\AA$ 미만인 경우의 산란 비율에 비하여 급격한 증가를 나타냄을 알 수 있었으며, 기판의 표면거칠기가 낮은 경우 반사경의 산란은 기판의 표면거칠기보다 반사경을 구성하는 박막의 미세구조에 의존하는 것으로 판단되었다. 한편 반사경 중에서 가장 작은 산란은 2.1 ppm이었고, 이것은 표면거칠기 0.23$\AA$인 기판에 이온빔 스퍼터링 방법으로 제작되었다.

• 한국전자파학회논문지
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• 제16권11호
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• pp.1067-1074
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• 2005

원형 마이크로스트립 안테나를 기본 구조로 하고 단점인 표면파의 영향을 개선하기 위해 접지면에 광 밴드 갭 구조를 취하여 대역폭을 늘리고 안테나의 후방 방사를 줄였다. 또한 광 밴드 갭의 형태를 각기 달리하여 그에 따른 안테나 특성의 변화를 관찰하였다. 끝으로 유전체 사이에 비유전율이 유전체보다 낮은 공기층을 삽입하여 전체적인 비유전율을 낮게 만들어 작은 크기로 높은 응답 주파수 특성을 보였다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제55권12호
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• pp.601-605
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• 2006

The resistance-capacitance (RC) delay of signals through interconnection materials becomes a big hurdle for high speed operation of semiconductors which contain multi-layer interconnections in smaller scales with higher integration density. Low-k materials are applied to the inter-metal dielectric (IMD) materials in order to overcome the RC delay. Relaxation continuum (RCT) model that includes neutral-species transport model have developed to model the etching process in a capacitively coupled plasma (CCP) device. We present the parametric study of the modeling results of a two-frequency capacitively coupled plasma (2f-CCP) with $N_2/H_2$ gas mixture that is known as promising one for organic low-k materials etching. For the etching of low-k materials by $N_2/H_2$ plasma, N and H atoms have a big influence on the materials. Moreover the distributions of excited neutral species influence the plasma density and profile. We include the neutral transport model as well as plasma one in the calculation. The plasma and neutrals are calculated self-consistently by iterating the simulation of both species till a spatio-temporal steady state profile could be obtained.

• 한국전기전자재료학회논문지
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• 제24권10호
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• pp.803-806
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• 2011

1 mol% $Li_2O$ excess $0.9(Na_{0.52}K_{0.48})NbO_3-0.1LiTaO_3$ lead-free piezoelectric multilayer ceramic actuators were investigated to determine their aging properties. To reduce the thermal aging behavior, we applied a rectified unipolar electric field of 5 kV/mm to the specimen to accelerate the electric aging behavior. By employing a rectified unipolar electric field for the piezoelectric actuators, we could remove undesirable heating from the relaxation current in the motion of the ferroelectric domain. To accelerate the aging test, the applied electric fields had a frequency of 900 Hz. To have enough time for charging and discharging, we employed an accurate time constant to design the equivalent circuit model for the aging tester. To extract exact aging behavior, we measured the pseudo-piezoelectric coefficient before and after the aging process. We also measured the electro-mechanical coupling coefficient, the frequency-dependent dielectric permittivity, and the impedance to compare with fresh and aged specimen.

• 한국컴퓨터정보학회논문지
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• 제27권1호
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• pp.33-41
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• 2022

본 논문은 유전체 기판 상에 설계한 평면형 마이크로스트립 패치 안테나를 기술하였다. 5세대 이동통신 적용을 위하여 2가지 타입의 평면형 마이크로스트립 패치 안테나를 연구하였으며 한 타입은 일반적인 마이크로스트립 구조이며 다른 한 타입은 동축 프로브 급전의 적층된 마이크로스립 구조이다. 전자기적인 커플링 방식을 사용한 적층된 마이크로스트립 패치는 다층기판 구조에서 설계되었다. 본 논문에서 제안한 적층된 마이크로스트립 패치 안테나는 3.42GHz~3.70GHz 광대역의 5G 서비스 대역에서 양호한 결과를 나타냈다. 임피던스 대역폭(VSWR≤2)은 3.42GHz~3.78GHz에서 360MHz(10.28%)를 나타냈다. 본 논문의 적층된 마이크로스트립 패치 안테나의 설계를 통하여 5G 이동통신 중계 시스템에 적용가능성을 확인하였다.

• 한국전자파학회논문지
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• 제17권10호
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• pp.967-975
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• 2006

본 논문에서는 40 GHz 대역에서 동작하는 IEEE 802.16 고정 무선 통신을 위한 천이, 소형 TDD 송수신 모듈의 front-end 모듈을 설계하고 구현하는 방법을 제안한다. 제안된 모듈은 저손실과 소형화를 동시에 달성하기 위하여 캐비티 공정을 가지는 다층 LTCC 기술을 이용하여 제작되었다. 스위치의 입출력단에 와이어본드 정합회로의 설계 및 안테나와의 연결을 위한 도파관 천이 구조를 통해 저손실의 천이를 얻었으며, 기존 금속 도파관 필터를 대체한 유전체 도파관 필터를 사용함으로써 소형화를 달성하였다. 이를 구현하기 위해 유전율 7.1, 두께 100 um인 총 6층의 LTCC 기판을 사용하였으며 제작된 소형 front-end 모듈의 크기는 $30{\times}7{\times}0.8mm^3$이다. 그리고 송수신 삽입 손실 < 5.3 dB, 이미지 신호 제거 > 49 dB의 우수한 천이를 얻을 수 있었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.