• 국제초고층학회논문집
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• 제6권3호
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• pp.271-277
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• 2017

Safety, livability, and efficiency are the three prominent problems of tall buildings, which are also the severe challenges to designers. We proposed the idea of building the sky town to solve these problems, which can be summarized in two sentences, one is tall building multi-storised, and another one is vertical facilities municipal-infrastructurised. The tall building can be horizontally cut into several multi-storey buildings by some large platforms. The platform extends a certain width to block the fire from spreading. Tall buildings are connected together as a group. One of them is a traffic core, which is used for vertical transportation and MEP. It connects to traffic center such as metro, while most of the other tall buildings' cores can be very much released, so as to achieve maximum efficiency of floor usable area and to give good traffic organization. By combining traffic core, platforms, and multi-storey buildings' inner traffic, a transportation network is formed. Finally, we refer to the design of Raffles City Chongqing to make a sketch of sky town.

• 대한임베디드공학회논문지
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• 제12권1호
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• pp.1-10
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• 2017

Recently, with the ever-increasing complexity of industrial robot systems, it has been greatly attention to adopt a multi-core based motion controller with high cost-performance ratio. In this paper, we propose a software architecture that aims to utilize the computing power of multi-core processors. The key concept of our architecture is to use shared memory for the interplay between threads running on separate processor cores. And then, we have integrated our proposed architecture with an industrial standard compliant IDE for automatic code generation of motion runtime. For the performance evaluation, we constructed a test-bed consisting of a motion controller with Preempt-RT Linux based dual-core industrial PC and a 3-axis industrial robot platform. The experimental results show that the actuation time difference between axes is 10 ns in average and bounded up to 689 ns under $1000{\mu}s$ control period, which can come up with real-time performance for industrial robot.

• 전기전자학회논문지
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• 제15권3호
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• pp.255-260
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• 2011

본 논문은 허프 변환을 이용한 차선 검출 알고리즘의 병렬화 기법을 제안한다. 허프 변환은 영상의 모든 위치에 존재 가능한 모든 후보 ${\Theta}$ 들에 대해 ${\rho}$ 값을 구해야 하므로 연산량이 많기 때문에 연산에 많은 시간이 소요되는 단점이 있다. 이를 멀티코어 환경에서 병렬 처리하는 구조를 제안 한다. 또한 허프 변환 이외에도 전처리 과정에 해당하는 노이즈 제거와 에지 검출도 병렬 처리 하였다. 제안하는 알고리즘은 기존 알고리즘에 비해 5.17배의 성능 향상이 있다.

• Journal of Platform Technology
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• 제10권2호
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• pp.3-9
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• 2022

본 논문에서는 멀티코어 프로세서 및 매니코어 프로세서에서의 스캐터 통신 성능을 최대화 하기 위하여 프로세싱 노드의 통신채널 상태를 고려하는 기법을 32개 코어로 구성된 멀티코어 프로세서에 적용하였다. 기존의 스캐터 알고리즘은 프로세싱 노드들의 통신채널 상태를 확인할 수 없기 때문에 일반적으로 초기 셋팅 된 전송순서에 따라서 통신을 수행한다. 이 경우 프로세서 내부의 모든 프로세싱 노드에서 기존 수행 중인 통신이 종료된 후에야 스캐터 통신이 시작되는데, 이때 발생하는 전송 대기 시간을 줄임으로서 스캐터 통신 성능을 향상 시킬 수 있다. 본 기법에 의하여 스캐터 통신 성능이 향상되었고, BFM 시뮬레이션을 통하여 기존 알고리즘 대비 최대 78.93%의 성능 향상이 있음을 확인하였다.

• 디지털산업정보학회논문지
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• 제15권4호
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• pp.85-92
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• 2019

This paper presents a SDR-based Long Term Evolution Advanced (LTE-A) Physical Downlink Shared Channel (PDSCH) decoder using a multicore Digital Signal Processor (DSP). For decoder implementation, multicore DSP TMS320C6670 is used, which provides various hardware accelerators such as turbo decoder, fast Fourier transformer and Bit Rate Coprocessors. The TMS320C6670 is a DSP specialized in implementing base station platforms and is not an optimized platform for implementing mobile terminal platform. Accordingly, in this paper, the hardware accelerator was changed to the terminal implementation to implement the LTE-A PDSCH decoder supporting the multi-antenna and the functions not provided by the hardware accelerator were implemented through core programming. Also pipeline using multicore was implemented to meet the transmission time interval. To confirm the feasibility of the proposed implementation, we verified the real-time decoding capability of the PDSCH decoder implemented using the LTE-A Reference Measurement Channel (RMC) waveform about transmission mode 2 and 3.

• Nuclear Engineering and Technology
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• 제49권6호
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• pp.1339-1345
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• 2017

In the framework of the EU funded project NURESAFE, the subchannel code CTF and the neutronics code DYN3D were integrated and coupled on the NURESIM platform. The developments achieved during this 3-year project include assembly-level and pin-by-pin multiphysics thermal hydraulics/neutron kinetics coupling. In order to test this coupling, a PWR rod ejection transient was simulated on a MOX/UOX minicore. The transient is simulated using two different models of the minicore. In the first simulation, both codes model the core with an assembly-wise resolution. In the second simulation, a pin-by-pin fuel-centered model is used in CTF for the central assembly, and a pin power reconstruction method is applied in DYN3D. The analysis shows the influence of the different models on global parameters, such as the power and the average fuel temperature, but also on local parameters such as the maximum fuel temperature.

• 한국컴퓨터정보학회논문지
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• 제16권6호
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• pp.11-20
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• 2011

본 논문에서는 DVFS 기능을 제공하는 멀티코어 프로세서 상에서 실시간 비디오 태스크의 에너지 소모량을 최소화하는 최적 스케쥴링 기법을 제안한다. 제안된 스케쥴링 기법은 멀티코어의 병렬처리 기법을 활용하도록 적절한 수의 멀티코어들을 태스크의 수행에 할당하고, 사용되지 않는 코어들의 전원을 끄며, 실시간 태스크의 데드라인을 만족하는 최저 클락 주파수를 배정한다. 단일 코어에서 태스크를 실행하는 기존 방법과 그리고 모든 코어들에서 태스크를 실행하는 기존 방법을 제안된 스케쥴링 기법과 비교하는 실험 결과에서, 제안된 스케쥴링 기법이 기존 방법들의 에너지 소모량을 각각 최대 67%, 89% 감소시킴을 확인하였다.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2010년도 한국컴퓨터종합학술대회논문집 Vol.37 No.1(A)
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• pp.347-348
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• 2010

• STI Policy Review
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• 제5권1호
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• pp.57-74
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• 2014

This review organises the fragmented management literature on platform business according to a conceptual map and a meta-theoretical scheme. Since the early 2000s, numerous researchers have examined platform business and two-sided networks with platform business and strategy being an important business innovation model for many industries, creating value primarily by enabling direct interactions. Platforms such as Google or Amazon contain a common set of rules and components in most user transactions. Thirty-two core papers and books on Strategic Management Journal, Industrial Economics and Operation Management-related disciplines are reviewed, with further observations on how cumulative research streams on the platform are carried out independently from each academic perspective. The first of the two arguments in this paper is that because interactive relationships bridge the platform and stakeholders such as end-users and developers, it is crucial for platform companies to be aware of their relationship with stakeholders in order to support and sustainably provide content to their platform. The second is that integrative perspectives are essential due to the low number of interdisciplinary investigations conducted thus far. The paper's final section deals with implications for theory and practice, concluding that integrative studies and interactive relationship studies should be the main research streams in future platform research.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제10권6호
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• pp.2648-2668
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• 2016

Modern mobile devices are equipped with various accelerated processing units to handle computationally intensive applications; therefore, Open Computing Language (OpenCL) has been proposed to fully take advantage of the computational power in heterogeneous systems. This article introduces a parallel software decoder of Low Density Parity Check (LDPC) codes on an embedded heterogeneous platform using an OpenCL framework. The LDPC code is one of the most popular and strongest error correcting codes for mobile communication systems. Each step of LDPC decoding has different parallelization characteristics. In the proposed LDPC decoder, steps suitable for task-level parallelization are executed on the multi-core central processing unit (CPU), and steps suitable for data-level parallelization are processed by the graphics processing unit (GPU). To improve the performance of OpenCL kernels for LDPC decoding operations, explicit thread scheduling, vectorization, and effective data transfer techniques are applied. The proposed LDPC decoder achieves high performance and high power efficiency by using heterogeneous multi-core processors on a unified computing framework.