• The KIPS Transactions:PartA
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• v.17A no.6
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• pp.265-274
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• 2010

As the process technology scales down and integration densities continue to increase, interconnection has become one of the most important factors in performance of recent multi-core processors. Recently, to reduce the delay due to interconnection, 3D architecture has been adopted in designing multi-core processors. In 3D multi-core processors, multiple cores are stacked vertically and each core on different layers are connected by direct vertical TSVs(through-silicon vias). Compared to 2D multi-core architecture, 3D multi-core architecture reduces wire length significantly, leading to decreased interconnection delay and lower power consumption. Despite the benefits mentioned above, 3D design technique cannot be practical without proper solutions for hotspots due to high temperature. In this paper, we propose three floorplan schemes for reducing the peak temperature in 3D multi-core processors. According to our simulation results, the proposed floorplan schemes are expected to mitigate the thermal problems of 3D multi-core processors efficiently, resulting in improved reliability. Moreover, processor performance improves by reducing the performance degradation due to DTM techniques. Power consumption also can be reduced by decreased temperature and reduced execution time.

• Journal of Communications and Networks
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• v.7 no.3
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• pp.377-384
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• 2005

The purpose of this research is to develop and evaluate a traffic engineering architecture that uses local state information. This architecture is applied to an Internet protocol radio access network (RAN) that uses multi-protocol label switching (MPLS) and differentiated services to support mobile hosts. We assume mobility support is provided by a protocol such as the hierarchical mobile Internet protocol. The traffic engineering architecture is router based-meaning that routers on the edges of the network make the decisions onto which paths to place admitted traffic. We propose an algorithm that supports the architecture and uses local network state in order to function. The goal of the architecture is to provide an inexpensive and fast method to reduce network congestion while increasing the quality of service (QoS) level when compared to traditional routing and traffic engineering techniques. We use a number of different mobility scenarios and a mix of different types of traffic to evaluate our architecture and algorithm. We use the network simulator ns-2 as the core of our simulation environment. Around this core we built a system of pre-simulation, during simulation, and post-processing software that enabled us to simulate our traffic engineering architecture with only very minimal changes to the core ns-2 software. Our simulation environment supports a number of different mobility scenarios and a mix of different types of traffic to evaluate our architecture and algorithm.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.4
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• pp.251-257
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• 2016

The multi-core technology has become pervasive in embedded systems. An implementation of the Doppler Beam Sharpening algorithm that improves the azimuth resolution by using doppler frequency shift is possible only in multi-core environment because of the amount of calculation. In this paper, we design of multi-core architecture for a real time implementation of DBS algorithm. And based on designed structure, we produce a DBS image on P4080 board.

• Journal of IKEEE
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• v.15 no.3
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• pp.255-260
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• 2011

In this paper, we propose a parallelization technique in lane detection by using Hough transform. Hough transform has a weakness that it has a lot computation quantity, because it has to compute ${\rho}$ value in all candidate ${\Theta}$ to be detected in an image. We propose an architecture of parallel processing for this transform in a multi-core environment. The parallel processing has application to Hough transform as well as noise reduction and edge detection. This proposed architecture has 5.17 times improvement in performance compare to the existing algorithm.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.4
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• pp.289-293
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• 2016

As more mobile devices are equipped with multi-core CPUs and are required to execute many compute-intensive multimedia applications, it is important to optimize the systems, considering the underlying parallel hardware architecture. In this paper, we implement and optimize ray-tracing application tailored to a given mobile computing platform with multiple heterogeneous processing elements. In this paper, a lightweight ray-tracing application is specified and implemented in Kahn process network (KPN) model-of-computation, which is known to be suitable for the description of real-time applications. We take an open-source C/C++ implementation of ray-tracing and adapt it to KPN description in the Distributed Application Layer framework. Then, several possible configurations are evaluated in the target mobile computing platform (Exynos 5422), where eight heterogeneous ARM cores are integrated. We derive the optimal degree of parallelism and a suitable distribution of the replicated tasks tailored to the target architecture.

• Journal of Aerospace System Engineering
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• v.13 no.5
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• pp.1-8
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• 2019

Recently, avionics has been migrating from a federated architecture to an integrated modular architecture based on a multi-core to reduce the number of systems, weight, power consumption, and platform redundancy. The volume of data which must bo provided to the pilot through the display device has increased, because an integrated single device performs multiple functions. For this reason, the volume of data processed by the graphic processor within a fixed operation period has increased. In this paper, we provide a multi-core-based rendering engine in to perform more graphics processing within a fixed operation period. We assume the proposed method uses a multi-core-based partitioning operating system using the AMP (Asymmetric Multi-Processing) architecture.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.540-543
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• 2013

This paper describes an implementation of a unified ALU on multi-core GPGPU based on SIMT architecture. Our unified ALU can operate conditional branch instructions, data movement instructions, integer arithmetic instructions and floating-point arithmetic instructions. Since multi-core GPGPU contains a lot of ALU for parallel processing of various types, the main point of this paper is to design the minimum size ALU by unifying similar processing of each operations on circit level. All instrunctions were tested by making a test program. And we compare this results with results of CPU operations to verify our ALU. Our unified ALU's gate size is approximately 20,000 and the maximum operation frequency is 430MHz.

• Journal of Digital Contents Society
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• v.19 no.6
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• pp.1219-1224
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• 2018

Nowaday, smart mobile devices on Internet of Things are required to process and deliver greate amount of data in real-time. Therefore, heterogeneous mult-core architecture such the big.LITTLE core architecture, which shows high energy conservation while guaranteeing high performance, are widely employed on up to date smart mobile devices. The LITTLE cores should be highly utilized to gain higher energy conservation because LITTLE cores have much higher energy efficiency than big cores. In this paper, we propose a core selection algorithm, which tries to firstly assign a real-time task on a LITTLE core rather a big core while the task can be finished within its own deadline. We also perform simulation as performance evaluation to show that our proposed algorithm shows higher energy conservation while guaranteeing the required performance.

• Journal of Korea Society of Industrial Information Systems
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• v.27 no.6
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• pp.69-75
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• 2022

We propose energy-efficient scheduling considering real-time constraints and energy efficiency in smart mobile with heterogeneous multi-core structure. Recently, high-performance applications such as VR, AR, and 3D game require real-time and high-level processings. The big.LITTLE architecture is applied to smart mobiles devices for high performance and high energy efficiency. However, there is a problem that the energy saving effect is reduced because LITTLE cores are not properly utilized. This paper proposes a heterogeneous multi-core assignment technique that improves real-time performance and high energy efficiency with big.LITTLE architecture. Our proposed method optimizes the energy consumption and the execution time by predicting the actual task execution time using SVM (Support Vector Machine). Experiments on an off-the-shelf smartphone show that the proposed method reduces energy consumption while ensuring the similar execution time to legacy schemes.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.6 s.324
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• pp.69-78
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• 2004

This paper proposes architecture and characteristics of a multi-ring based optical network with single-hop between edge nodes using the concept of circuit switching and multi-wavelength label switching to solve delay problem caused by applying crossconnectors as transit nodes in the wavelength division multiplexing(WDM) network. We suggest multi-ring based architecture composed single and multiple wavelength-bands with multi-wavelength labels, and analyze characteristics of two models. To avoid the packet collision in output ports of edge nodes due to output contention, the static and dynamic allocation scheme, which packets are allocated in time slots, is provided. Based on our analysis, it shows that delay only occur in not core nodes but edge nodes in the proposed architecture. In addition, we evaluate the probabilities of delay, packet loss, and call blocking in the proposed optical packet network.