• Proceedings of the Optical Society of Korea Conference
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• 2007.07a
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• pp.223-224
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• 2007

광기록의 역사는 1980년대초 Sony와 Philips가 공동 개발한 CD (compact disc: 640MB)의 출현으로부터 시작하여 1996년의 DVD (digital versatile disc: 4.7GB)를 거쳐 최근의 BD (Blu-ray disc: >20GB)에까지 이르고 있다. Read-only memory, recordable, rewritable 등 다양한 저장 및 재생방식이 존재하는데, 이는 레이저 조사에 의한 기록매체의 특성변화의 가역성 (reversibility)에 의존하므로 저장 및 재생방식에 따라 저장매체 또한 다르게 된다. 기록용량의 증가는 레이저의 파장이 짧아지고 동시에 사용된 렌즈의 개구수 (NA: Numerical aperture)가 증가함에 따른 빔 spot size의 감소에 기인한다. 회절한계를 극복하여 빔의 spot size를 줄이고자 하는 연구는 현재도 전세계적으로 활발히 이루어지고 있고 이러한 노력의 일환으로 어느 정도의 추가적인 저장용량 증가는 가능할 수 있으나, 2차원 방식으로는 대용량 광정보기록 (수백 GB ${\sim}$ TB급)의 실현은 불가능하다는 것이 일반적인 예상이다. 한편 장기적으로 기존의 2차원 정보기록방식을 대체하고 저장용량을 획기적으로 증가시킬 수 있는 bit-type 3차원 광정보기록의 개념이 1990년을 전.후로 처음으로 제시되었다. 이는 2차원 bit 정보가 수십 내지 수백 개의 다층 (multi-layer) 형태로 기록되는 방식인데, 그동안 산업체의 관심이 상대적으로 높지 않았던 이유는 영화, 음악 등 엔터테인먼트 시장성 확대를 위해 Blu-ray disc나 HD-DVD에 대한 연구개발에 치중해왔기 때문이다. 하지만 최근 급변하는 정보시스템 서비스 환경 속에서 정보유통량이 기하급수적으로 증가하고 있고 개인이 취급하는 정보량도 2010년경에는 수백 GB 단위가 될 것으로 예상되고 있으며 디지털 방송, 네트워크를 기반으로 한 서비스 수요 뿐 만 아니라 전자도서관이나 VOD (Video on Demand) 서비스 사업에 필수적인 수 TB급의 대용량 저장장치에 대한 수요 또한 크게 증가할 것으로 전망된다. 이에 따라 점차 그 물리적 한계에 다다르고 있는 기존의2차원 정보저장방식을 대체하고 저장용량을 획기적으로 증가시킬 수 있는3차원 정보기록(> $10^{13}$ $bits/cm^3$)에 대한 필요성이 대두된다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.963-972
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• 2002

An 8192-point pipelined FFT/IFFT processor core is designed, which can be used in multi-carrier modulation systems such as DUf-based VDSL modem and OFDM-based DVB system. In order to improve the signal-to-quantization-noise ratio (SQNR) of FFT/IFFT results, two-step convergent block floating-point (TS_CBFP) scaling is employed. Since the proposed TS_CBFP scaling does not require additional buffer memory, it reduces memory as much as about 80% when compared with conventional CBFP methods, resulting in area-and power-efficient implementation. The SQNR of about 60-㏈ is achieved with 10-bit input, 14-bit internal data and twiddle factors, and 16-bit output. The core synthesized using 0.25-$\mu\textrm{m}$ CMOS library has about 76,300 gates, 390K bits RAM, and twiddle factor ROM of 39K bits. Simulation results show that it can safely operate up to 50-㎒ clock frequency at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. It was verified by Xilinx FPGA implementation.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.672-675
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• 1997

This paper proposes a structure of the control system for the step & scan exposure tool. The step & scan exposure tool is used for the manufacturing process of the semiconductor DRAM memory of giga bit. The control system employs the VME bus instead of the conventional ISA bus so that all control signals and data can be managed separately by the 4 VME-PCs for fast and fault-free flow of signals for multi-tasking. A high speed I/O card is equipped for the real-time monitoring and control of the sub module equipment. Then all the subsystems are integrated and aligned for the operation of the step & scan exposure tool with the VME bus and, I/O card.

• Journal of Sensor Science and Technology
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• v.30 no.4
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• pp.223-228
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• 2021

This work presents a low-power CMOS image sensor (CIS) with a multi-column-parallel (MCP) readout structure while focusing on improving its performance compared to previous works. A delta readout scheme that utilizes the image characteristics is optimized for the MCP readout structure. By simply alternating the MCP readout direction for each row selection, additional memory for the row-to-row delta readout is not required, resulting in a reduced area of occupation compared to the previous work. In addition, the bias current of a pre-amplifier in a successive approximate register (SAR) analog-to-digital converter (ADC) changes according to the operating period to improve the power efficiency. The prototype CIS chip was fabricated using a 0.18-㎛ CMOS process. A 160 × 120 pixel array with 4.4 ㎛ pitch was implemented with a 10-bit SAR ADC. The prototype CIS demonstrated a frame rate of 120 fps with a total power consumption of 1.92 mW.

• Proceedings of the Optical Society of Korea Conference
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• 2000.02a
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• pp.168-169
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• 2000

We have tried to enhance the density of the near-field optical memory and to improve the recording/readout speed. The current optical memory has the limitation in both density and speed. This barrier due to the far-field nature can be overcome by the use of the near-field$^{(1)}$ . The optical data storage density can be increased by reducing the size of the nanometric aperture where the near-field is obtained. To fabricate the aperture in precise dimension, we applied the orientation-dependent / anisotropic etching property of crystal Si often employed in the field of MEMS$^{(2)}$ . And so we fabricated the 10$\times$10 aperture array. This array will be also the indispensable part for speeding up. One will see the possibility of the multi-tracking pickup in the phase changing type memory through this array$^{(3)}$ . This aperture array will be expected to write the bit-mark whose size is about 100nm. We will show the recent result obtained. (omitted)

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.6
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• pp.540-549
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• 2013

An adaptive non-uniform quantization scheme is proposed for soft-decision error correction in NAND flash memory. Even though the conventional maximizing mutual information (MMI) quantizer shows the optimal post-FEC (forward error correction) bit error rate (BER) performance, this quantization scheme demands heavy computational overheads due to the exhaustive search to find the optimal parameter values. The proposed quantization scheme has a simple structure that is constructed by only six parameters, and the optimal values of them are found by maximizing the mutual information between the input and the output symbols. It is demonstrated that the proposed quantization scheme improves the BER performance of soft-decision decoding with only small computational overheads.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.61-71
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• 2014

As the occupancy rate of the flash memory increases in the storage media market for the embedded system and the semi-conductor industry grows, the demand and supply of flash memory is increasing by a big margin. They are especially used in large quantity in the smart phones, tablets, PC, SSD and Soc(System on Chip) etc. The flash memory is divided into the NOR type and NAND type according to the cell arrangement structure and the NAND type is divided into the SLC(Single Level Cell) and MLC(Multi Level Cell) according to the number of bits that can be stored in each cell. Many tests have been performed on NOR type such as BIST(Bulit-In Self Test) and BIRA(Bulit-In Redundancy Analysis) etc, but there is little study on the NAND type. For the case of the existing BIST, the test can be proceeded using external equipments like ATE of high price. However, this paper is an attempt for the improvement of credibility and harvest rate of the system by proposing the BIST for the MLC NAND type flash memory of Finite State Machine structure on which the pattern test can be performed without external equipment since the necessary patterns are embedded in the interior and which uses the MLC NAND March(x) algorithm and pattern which had been proposed for the MLC NAND type flash memory.

• The Journal of the Acoustical Society of Korea
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• v.31 no.2
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• pp.93-99
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• 2012

For speech coding, a vocal tract is modeled using Linear Predictive Coding (LPC) coefficients. The LPC coefficients are typically transformed to Line Spectral Frequency (LSF) parameters which are advantageous for linear interpolation and quantization. If multidimensional LSF data are quantized directly using Vector-Quantization (VQ), high rate-distortion performance can be obtained by fully utilizing intra-frame correlation. In practice, since this direct VQ system cannot be used due to high computational complexity and memory requirement, Split VQ (SVQ) is used where a multidimensional vector is split into multilple sub-vectors for quantization. The LSF parameters also have high inter-frame correlation, and thus Predictive SVQ (PSVQ) is utilized. PSVQ provides better rate-distortion performance than SVQ. In this paper, to implement the optimal predictors in PSVQ for voice storage devices, we propose Multi-Frame AR-model based SVQ (MF-AR-SVQ) that considers the inter-frame correlations with multiple previous frames. Compared with conventional PSVQ, the proposed MF-AR-SVQ provides 1 bit gain in terms of spectral distortion without significant increase in complexity and memory requirement.

• The Journal of the Acoustical Society of Korea
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• v.23 no.3
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• pp.262-267
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• 2004

AMR-WB (Adaptive Multi Rate Wideband) speech codec, the most recent voice codec standardized by 3GPP, has the wider audio bandwidth of 50∼7000 Hz and operates on nine speech coding bit rates between 6.60 and 23.85 kbit/s. This Paper presents the real-time implementation of AMR-WB speech codec by using a 16 bit fixed-point TeakLite DSP. The implemented AMR-WB codec requires the complexity of 52.2 MIPS at 23.85 kbit/s mode and also needs the program memory of 17.9 kwords, data RAM of 11.8 kwords, and data ROM of 10.1kwords. It was verified through passing the all test vectors provided by 3GPP with maintaining bit exactness. Stable operations on the real-time testing board were also proved without any distortions and delays for the audio in/out.

• The Journal of the Acoustical Society of Korea
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• v.21 no.7
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• pp.648-655
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• 2002

This paper describes implementation of a multi-channel G.723.1 Annex A (G.723.1A) focused on code optimization using a high performance general purpose Digital Signal Processor (DSP), To implement a multi-channel G.723.1A functional complexities of the ITU-T G.723.1A fixed-point C-code are measures an analyzed. Then we sort and optimize C functions in complexity order. In parallel with optimization, we verify the bit-exactness of the optimized code using the ITU-T test vectors. Using only internal memory, the optimized code can perform full-duplex 17 channel processing. In addition, we further increase the number of available channels per DSP into 22 using fast codebook search algorithms, referred to as bit -compatible optimization.