• Journal of IKEEE
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• v.23 no.1
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• pp.326-329
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• 2019

Gallium nitride(GaN) has been a superior candidate for the next generation power electronics. As GaN-on-Si substrate technology is mature, there has been new demand for monolithic integration of GaN technology with Si CMOS devices. In this work, (110)Si CMOS process was developed and the fabricated devices were evaluated in order to confirm the feasibility of utilizing domestic foundry facility for monolithic integration of Si CMOS and GaN power devices.

• Journal of information and communication convergence engineering
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• v.12 no.3
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• pp.186-192
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• 2014

Monolithic three-dimensional integrated chips (3D ICs) are an emerging technology that offers an integration density that is some orders of magnitude higher than the conventional through-silicon-via (TSV)-based 3D ICs. This is due to a sequential integration process that enables extremely small monolithic inter-tier vias (MIVs). For a monolithic 3D memory, we first explore the static random-access memory (SRAM) design. Next, for digital logic, we explore several design styles. The first is transistor-level, which is a design style unique to monolithic 3D ICs that are enabled by the ultra-high-density of MIVs. We also explore gate-level and block-level design styles, which are available for TSV-based 3D ICs. For each of these design styles, we present techniques to obtain the graphic database system (GDS) layouts, and perform a signoff-quality performance and power analysis. We also discuss various challenges facing monolithic 3D ICs, such as achieving 50% footprint reduction over two-dimensional (2D) ICs, routing congestion, power delivery network design, and thermal issues. Finally, we present design techniques to overcome these challenges.

• ETRI Journal
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• v.29 no.6
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• pp.811-813
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• 2007

We report on a ridge waveguide laser diode with laterally tapered waveguides fabricated in a single growing step using a double patterning method. In this structure, nearly constant output power is obtained with the change of the lower tapered waveguide width, and the facet power ratio of 1.4 to 1.5 is observed over the current range. The asymmetric facet power property is also investigated.

• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.369-374
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• 2016

This paper presents a design procedure of an integrated inductor with a magnetic core for power converters. This procedure considerably reduces design time and effort. The proposed design procedure is verified by the development of an inductor model dedicated to the monolithic integration of DC-DC converters for portable applications. The numerical simulation based on the FEM (finite elements method) shows that 3D modeling of the integrated inductor allows better estimation of the electrical parameters of the desired inductor. The optimization of the electrical parameter values is based on the numerical analysis of the influence of the geometric parameters on the electrical characteristics of the inductor. Using the VHDL-AMS language, implementation of the integrated inductor in a micro Buck converter demonstrate that simulation results present a very promising approach for the monolithic integration of DC-DC converters.

• Progress in Superconductivity and Cryogenics
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• v.19 no.4
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• pp.18-21
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• 2017

We report a method for improving heat exchange between cryo-cooled large-power-dissipation devices and liquid cryogen. Micro-machined monolithic heat sinks were fabricated on a high integration density superconducting Josephson device, and studied for their effect on cooling the device. The monolithic heat sink showed a significant enhancement of cooling capability, which markedly improved the device operation under large dc- and microwave power dissipation. The detailed mechanism of the enhancement still needs further modeling and experiments in order to optimize the design of the heat sink.

• Journal of electromagnetic engineering and science
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• v.18 no.2
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• pp.101-107
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• 2018

The impedance bandwidth and radiation characteristics of an aperture-coupled microstrip line-fed patch antenna (ACMPA) with a high permittivity (${\varepsilon}_r=10$) feed substrate suitable for integration with a monolithic microwave integrated circuit (MMIC) are investigated for various feed substrate thicknesses through an experiment and computer simulation. The impedance bandwidth of an ACMPA with a high permittivity feed substrate increases as the feed substrate thickness decreases. Furthermore, the front-to-back ratio of an ACMPA with a high permittivity feed substrate increases and the cross-polarization level decreases as the feed substrate thickness decreases. As the impedance bandwidth of an ACMPA with a high permittivity feed substrate increases and its radiation characteristics improve as the feed substrate thickness decreases, the ACMPA configuration becomes suitable for integration with an MMIC.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.06a
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• pp.593-594
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• 2008

• Electronics and Telecommunications Trends
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• v.36 no.3
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• pp.12-22
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• 2021

Since the technical realization of self-aligned planar complementary metal-oxide-semiconductor field-effect transistors in 1960s, semiconductor manufacturing has aggressively pursued scaling that fruitfully resulted in tremendous advancement in device performances and realization of features sizes smaller than 10 nm. Due to many intrinsic material and technical obstacles, continuing the scaling progress of semiconductor devices has become increasingly arduous. As an effort to circumvent the areal limit, stacking devices in a three-dimensional fashion has been suggested. This approach is commonly called monolithic three-dimensional (M3D) integration. In this work, we examined technical issues that need to be addressed and overcome to fully realize energy efficiency, short latency and cost competency. Full-fledged M3D technologies are expected to contribute to various new fields of artificial intelligence, autonomous gadgets and unknowns, which are to be discovered.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• ETRI Journal
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• v.26 no.1
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• pp.61-64
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• 2004

We have explored the fabrication of an InP/InGaAs single heterojunction bipolar transistor (HBT) and a wave guide p-i-n photodiode (PD) on two kinds of double stacked layers for the implementation of an optoelectronic millimeter-wave monolithic integrated circuit (OEMMIC). We applied a photosensitive polyimide for passivation and integration to overcome the large difference between the HBT and PD layers of around $3{\mu}m$. Our experiment showed that the RF characteristics of the HBT were dependent on the location of the PD layer, while the dc performances of the HBTs and PDs were independent of the type of stacked layer used. The $F_t$ and $F_{max}$ of the HBTs on the HBT/PD stacked layer were 10% lower than those of the HBTs on the PD/HBT stacked layer.