• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.24-26
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• 2000

본 논문에서는 RSA 암호 시스템의 핵심 과정인 모듈로 멱승(Modular Exponentiation) 연산에 대한 새로운 하드웨어 구조를 제시한다. 기존의 몽고메리 알고리즘을 사용하였지만 다른 논문들이 Dependence Graph를 수직으로 매핑(Mapping)한 것과는 달리 여기서는 수평으로 매핑하여 1차원 선형 어레이(linear array) 구조를 구성하였다. 본 논문에서 사용한 방법의 장점은 결과가 시리얼(serial)로 나와서 바로 입력으로 들어갈 수 있기 때문에 100%의 처리율(throughput)을 이룰 수 있고, 수직 매핑 방식에 비해 절반의 클럭 횟수로 연산을 해낼 수 있다는 점이다. 또한 내부 계산 구조의 지역성(Locality) , 규칙성(Regularity) 및 모듈성(Modularity) 등으로 인해 실시간 고속 처리를 위한 VLSI 구현에 적합하다.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2002.06a
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• pp.190-194
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• 2002

Multiplication in Galois Field GF(2/sup m/) is a primary operation for many applications, particularly for public key cryptography such as Diffie-Hellman key exchange, ElGamal. The current paper presents a new architecture that can process Montgomery multiplication over GF(2/sup m/) in m clock cycles based on cellular automata. It is possible to implement the modular exponentiation, division, inversion /sup 1)/architecture, etc. efficiently based on the Montgomery multiplication proposed in this paper. Since cellular automata architecture is simple, regular, modular and cascadable, it can be utilized efficiently for the implementation of VLSI.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.10 no.1
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• pp.89-97
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• 2000

공개키 암호 시스템 중에서 가장 널리 사용되는 RSA 암호 시스템은 키의 분배와 권리가 용이하고, 디지털 서명이 가능한 장점이 있으나, 암호화와 복호화 과정에서 512 비트 이상의 큰 수에 대한 멱승과 모듈라 감소 연산이 요구되기 때문에 처리 속도의 지연이 큰 문제가 되므로 모듈라 멱승 연산의 고속 처리가 필수적이다. 따라서 본 논문에서는 몫을 추정하여 중간 곱의 크기를 제한하는 interleaved 모듈라 곱셈 기법을 이용하여 모듈라 멱승 연산을 수행하는 고속 RSA 암호 칩을 VHDL을 이용하여 모델링하고 Faraday FG7000A 라이브러리를 이용하여 합성하고 타이밍 검증하여 단일 칩 IC로 구현하였다. 구현된 암호 칩은 75,000 게이트 수준으로 합성되었으며, 동작 주파수는 50MHz이고 1회의 RSA 연산을 수행하는데 소요되는 전체 클럭 사이클은 0.25M이며 512비트 당 처리 속도는 102.4Kbit/s였다.

• Journal of Korea Society of Digital Industry and Information Management
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• v.18 no.1
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• pp.1-9
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• 2022

Galois field arithmetic is important in error correcting codes and public-key cryptography schemes. Hardware realization of these schemes requires an efficient implementation of Galois field arithmetic operations. Multiplication is the main finite field operation and designing efficient multiplier can clearly affect the performance of compute-intensive applications. Diverse algorithms and hardware architectures are presented in the literature for hardware realization of Galois field multiplication to acquire a reduction in time and area. This paper presents a low complexity semi-systolic multiplier to facilitate parallel processing by partitioning Montgomery modular multiplication (MMM) into two independent and identical units and two-level systolic computation scheme. Analytical results indicate that the proposed multiplier achieves lower area-time (AT) complexity compared to related multipliers. Moreover, the proposed method has regularity, concurrency, and modularity, and thus is well suited for VLSI implementation. It can be applied as a core circuit for multiplication and division/exponentiation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.1C
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• pp.87-92
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• 2006

An $AB^2$ modular operation is an efficient basic operation for the public key cryptosystems and various systolic architectures for $AB^2$ modular operation have been proposed. However, these architectures have a shortcoming for cryptographic applications due to their high area complexity. Accordingly, this paper presents an partitioned $AB^2$ systolic modular multiplier over GF($2^m$). A dependency graph from the MSB $AB^2$ modular multiplication algorithm is partitioned into 1/3 to get an partitioned $AB^2$ systolic multiplier. The multiplier reduces the area complexity about 2/3 compared with the previous multiplier. The multiplier could be used as a basic building block to implement the modular exponentiation for the public key cryptosystems based on smartcard which has a restricted hardware requirements.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.35-44
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• 2002

In this paper, an implementation method of RSA exponentiator based on Radix-$2^k$ modular multiplication algorithm is presented and verified. We use Booth receding algorithm to implement Radix-$2^k$ modular multiplication and implement radix-16 modular multiplier using 2K-byte memory and CSA(carry-save adder) array - with two full adder and three half adder delays. For high speed final addition we use a reduced carry generation and propagation scheme called pseudo carry look-ahead adder. Furthermore, the optimum value of the radix is presented through the trade-off between the operating frequency and the throughput for given Silicon technology. We have verified 1,024-bit RSA processor using Altera FPGA EP2K1500E device and Samsung 0.3$\mu\textrm{m}$ technology. In case of the radix-16 modular multiplication algorithm, (n+4+1)/4 clock cycles are needed and the 1,024-bit modular exponentiation is performed in 5.38ms at 50MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.2
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• pp.394-402
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• 2010

At a recent, enterprises based on online-service are established because of rapid growth of information network. These enterprises collect personal information and do customer management. If customers use a paid service, company send billing information to customer and customer pay it. Such circulation and management of information is big issue but most companies don't care of information security. Actually, personal information that was managed by largest internal open-market was exposed. For safe customer information management, this paper proposes the method that decrease load of RSA cryptography algorithm that is commonly used for preventing from illegal attack or hacking. The method for decreasing load was designed by Binary NAF Method and it can operates modular Exponentiation rapidly. We implemented modular Exponentiation algorithm using existing Binary Method and Windows Method and compared and evaluated it.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.5_6
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• pp.239-249
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• 2003

The secret sharing is the basic concept of the threshold cryptosystem and has an important position in the modern cryptography. At 1995, Jarecki proposed the proactive secret sharing to be a solution of existing the mobile adversary and also proposed the share renewal scheme for (k, n) threshold scheme. For n participants in the protocol, his method needs $O(n^2)$ modular exponentiation per one participant. It is very high computational cost and is not fit for the scalable cryptosystem. In this paper, we propose the efficient share renewal scheme that need only O(n) modular exponentiation per participant. And we prove our scheme is secure if less than img ${\frac{1}{2}}$ n-1 adversaries exist and they are static adversary.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.6
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• pp.29-39
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• 2007

RSA is one of the most popular public-key crypto-system in various applications. This paper addresses a high-speed RSA crypto-processor with modified radix-4 modular multiplication algorithm and Chinese Remainder Theorem(CRT) using Carry Save Adder(CSA). Our design takes 0.84M clock cycles for a 1024-bit modular exponentiation and 0.25M cycles for a 512-bit exponentiations. With 0.18um standard cell library, the processor achieves 365Kbps for a 1024-bit exponentiation and 1,233Kbps for two 512-bit exponentiations at a 300MHz clock rate.

• Journal of Korea Society of Industrial Information Systems
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• v.10 no.3
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• pp.57-63
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• 2005

Kim and Fenn et al. proposed two modular AB multipliers based on LFSR(Linear Feedback Shift Register) architecture. These multipliers use AOP, which has all coefficients with '1', as an irreducible polynomial. Thereby, they have good hardware complexity compared to the previous architectures. This paper proposes a modular $AB^2$ multiplier based on LFSR architecture and a modular exponentiation architecture to improve the hardware complexity of the Kim's. Our multiplier also use the AOP as an irreducible polynomial as the Kim architecture. Simulation result shows that our multiplier reduces the hardware complexity about $50\%$ in the perspective of XOR and AND gates compared to the Kim's. The architecture could be used as a basic block to implement public-key cryptosystems.